Design And Reuse

Monday, July 14, 2008

Synopsys Broadens DesignWare SATA Solution With Device IP

Synopsys, Inc.
(Nasdaq: SNPS), a world leader in software and IP for semiconductor design
and manufacturing, today announced the availability of the DesignWare(R)
SATA Device IP, for use in applications such as solid state drives, hard
disk drives and optical disk drives. Additionally, Synopsys' comprehensive,
silicon-proven DesignWare SATA IP solution consisting of Device, Host, PHY
IP in 90 nanometer (nm) and 65nm processes, and Verification IP (VIP) has
passed the SATA-IO Building Block interoperability testing, demonstrating
full SATA functionality from a single vendor. Synopsys provides a
comprehensive high quality IP solution helping designers reduce the risk
and cost of integrating the SATA interface into their system-on-chip (SoC)
designs.

The Synopsys DesignWare SATA Device IP supports transfer speeds of 1.5
Gb/sec and 3.0 Gb/sec with a roadmap to 6Gb/sec, making it ideal for
storage applications requiring high system performance. A proven component
of the Synopsys Eclypse(TM) low power solution, the IP implements multiple
aggressive power management features which can be utilized to lower the
power consumption of the end application. The inclusion of a well-defined,
DMA-based software programming interface helps designers achieve optimal
system performance while maintaining low latency and minimal software
overhead. Furthermore, the supplied example firmware helps reduce the
overall software development, integration and maintenance effort.

With the release of the SATA Device IP, Synopsys now offers designers a
comprehensive, silicon-proven and fully interoperable SATA IP solution
consisting of the Device, Host, PHY and Verification IP. The DesignWare
SATA Host Controller supports Native Command Queuing and Asynchronous
Notification in up to eight ports. The Host Controller is verified with the
industry-standard AHCI software drivers provided as part of the Linux and
Microsoft Windows Vista operating systems, enabling designers to ease
system-level integration. Complementing the Host and Device Controllers is
the robust, low power DesignWare SATA PHY, which includes unique built-in
diagnostics allowing on-chip visibility into the link performance and ATE
test vectors for at-speed production testing. The DesignWare Verification
IP helps designers quickly and efficiently create a comprehensive
SATA-based environment. In addition, the SATA Verification IP delivers up
to 5X performance improvement when used with Synopsys' VCS(R) simulation
tool and is VMM-enabled to help speed the development of powerful
SystemVerilog testbenches.

"SATA International Organization (SATA-IO) commends our member
companies who are advancing SATA technology by introducing new products
that incorporate the advantages of this popular storage interface," said
Tom Pratt, SATA-IO board representative. "Fast transfer rates, low cost and
efficient protocol have made SATA the mainstream storage interface of
choice."

"The requirement for mass storage devices is continuing to grow, with
solid state drives estimated to increase at a 76 percent CAGR from 2007 to
2012 (1)," said John Koeter, senior director of marketing for IP and
Services at Synopsys. "By providing a complete DesignWare SATA IP solution
that offers a strong combination of proven interoperability, low power, and
ease of integration features, Synopsys enables designers to integrate the
SATA interface into SoC designs with less risk and improved time to
market."

Availability

The complete DesignWare SATA IP solution including Device, Host, PHY in
130nm, 90nm and 65nm processes, and Verification is available now. For more
information please visit: http://www.synopsys.com/sata_solutions/

In addition, on July 31 Synopsys will sponsor a free webinar titled,
"Achieving Optimal Performance and Low Power for SATA Device Designs" To
register, please go to: http://www.synopsys.com/sata/



About DesignWare IP

Synopsys offers a broad portfolio of high-quality, silicon-proven
digital, mixed-signal and verification IP for system-on-chip designs. As a
leading provider of connectivity IP, Synopsys delivers the industry's most
complete solutions for widely used protocols such as USB, PCI Express,
SATA, Ethernet and DDR. The DesignWare IP is optimized for low power and is
an integral part of the Synopsys Eclypse low power solution. In addition to
connectivity IP, Synopsys offers SystemC transaction level models to build
virtual platforms for rapid, pre-silicon development of software. When
combined with a robust IP development methodology, extensive investment in
quality and comprehensive technical support, DesignWare IP enables
designers to accelerate time-to-market and reduce integration risk. For
more information on DesignWare IP, visit http://www.synopsys.com/designware

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design
automation (EDA), supplying the global electronics market with the
software, intellectual property (IP) and services used in semiconductor
design and manufacturing. Synopsys' comprehensive, integrated portfolio of
implementation, verification, IP, manufacturing and field-programmable gate
array (FPGA) solutions helps address the key challenges designers and
manufacturers face today, such as power and yield management,
system-to-silicon verification and time-to-results. These
technology-leading solutions help give Synopsys customers a competitive
edge in bringing the best products to market quickly while reducing costs
and schedule risk. Synopsys is headquartered in Mountain View, California,
and has more than 60 offices located throughout North America, Europe,
Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

(1) IDC, "Worldwide Solid State Drive 2008-2012 Forecast and Analysis:
Entering the No-Spin Zone," Doc # 212736, June 2008



Synopsys, DesignWare, Eclypse and VCS are registered trademarks or
trademarks of Synopsys, Inc. Any other trademarks or registered trademarks
mentioned in this release are the intellectual property of their respective
owners.

Editorial Contact:

Sheryl Gulizia
Synopsys, Inc.
650-584-8635
sgulizia@synopsys.com

Lisa Gillette-Martin
MCA, Inc.
650-968-8900 ext. 115
lgmartin@mcapr.com

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