More than one billion wireless devices are sold every year. This enormous volume, in combination with the hardware and software complexity of the devices, has given rise to an uncountable number of technical advances. Seemingly small changes of pennies per unit in manufacturing costs, or a slip in the delivery schedule, can add up to substantial dollar amounts when combined with the sheer volume of devices to be manufactured.
One technology gaining widespread acceptance within the wireless design community is the use of virtual prototypes throughout the design cycle. Wireless engineers are leveraging virtual prototypes of their system-on-chip designs to improve product quality and speed time to market. A virtual prototype can be an indispensable tool for performing early architectural analysis for throughput and power tradeoffs. Firmware developers can use virtual prototypes to develop and debug their software in advance of real silicon. In addition, virtual prototypes can be used to optimize the throughput of designs that have been built already.
Moving beyond spreadsheets
Until recently, architectural exploration was relatively ad hoc. Back-of-the-envelope calculations, combined with a few spreadsheets and years of design expertise, comprised the entire architectural flow for many chips and systems. This methodology is elegant in its simplicity but fails to deliver the architectural certainty required by most wireless apps.
A poorly designed architecture can present itself in many ways. The most visible evidence is that it doesn't meet its performance targets. Underperforming chips can sometimes be revived by creative firmware engineers and extra months in the lab. More often than not, slow chips are relegated to the trash heap.
The more common, and far less obvious, architectural failing is overdesign. The worst-case conditions of various spreadsheet components are added together--including those that would never occur together in the real world--and the architect generates a design exceeding specifications.
Overdesigned architectures have hidden costs associated with them. Expensive, high-speed memory may be used in cases where less expensive, slower components might have sufficed. The main processor clock running at 400 MHz might have run fine at 300 MHz instead. The ultimate price for an overdesigned architecture is typically seen in an end product that costs more and has a shorter battery life than competitive products. The problems resulting from overdesign may not be as obvious as those from underdesign, but the end result is not much different.
Virtual prototypes remove the guesswork from architectural decisions because the architect can explore multiple design scenarios and get an in-depth understanding of the real-world impacts of various design decisions and intellectual property (IP) selections. Analysis tools can be used to display such critical items as throughput, loading and latency. These results can be examined on a cycle-by-cycle basis and directly correlated with various hardware and software components. The data available from a virtual prototype can enable an architect to confidently make big decisions, such as which IP block to select, as well as seemingly smaller ones, such as what arbitration scheme to employ.
Thursday, October 30, 2008
1394-2008 High Performance Serial Bus Standard
The IEEE Standards Board recently approved the 1394-2008 specification. 1394-2008 combines all IEEE-1394 specifications developed since the audio-video multimedia standard was founded in 1994. The 1394-2008 High Performance Serial Bus Standard updates and revises all prior 1394 standards dating back to the original 1394-1995 version, and including 1394a, 1394b, 1394c, enhanced UTP, and the 1394 beta plus PHY-Link interface. It also incorporates the complete specifications for S1600 (1.6 Gigabit/second bandwidth) and for S3200, which provides 3.2 Gigabit/second speeds.
IEEE-1394, also known as FireWire and i.LINK, has been designed into a wide range of consumer, computer, industrial and other products since its inception, and is emerging as a powerful new standard for use in automotive entertainment systems.
The team dealt with errata remaining from prior specifications, and harmonized all message types, including fields that had been used in related specifications such as the 1394.1 bridging specification, and IDB-1394, which was developed as the original automotive entertainment standard. Not incorporated is work currently underway within the 1394 Trade Association working groups, including 1394 over coax and the new 1394-Automotive specification due later this summer.
IEEE-1394, also known as FireWire and i.LINK, has been designed into a wide range of consumer, computer, industrial and other products since its inception, and is emerging as a powerful new standard for use in automotive entertainment systems.
The team dealt with errata remaining from prior specifications, and harmonized all message types, including fields that had been used in related specifications such as the 1394.1 bridging specification, and IDB-1394, which was developed as the original automotive entertainment standard. Not incorporated is work currently underway within the 1394 Trade Association working groups, including 1394 over coax and the new 1394-Automotive specification due later this summer.
How to improve FPGA-based ASIC prototyping with SystemVerilog
Introduction
ASICs provide a solution for capturing high performance complex design concepts and preventing competitors from simply implementing comparable designs.
However, creating an ASIC is a high-investment proposition with development costs approaching $20M for a 90 nm ASIC/SoC design and expected to top $40M for a 45 nm SoC. Thus, increasingly, only a high-volume product can afford an ASIC.
Besides the increase in mask-set cost, total development cost is also increasing due to the reduced probability of getting the design right the first time. As design complexity continues to increase, surveys have shown that only about a third of today's SoC designs are bug-free in first silicon, and nearly half of all respins are reported as being caused by functional logic error(s). As a result, verification managers are now exploring ways to strengthen their functional verification methodologies.
Before starting on a true ASIC design, to demonstrate that concepts are sound and that designs can be implemented, a lower-cost method of using FPGAs to prototype ASIC designs as part of an ASIC verification methodology has been growing in popularity.
Prototyping ASIC designs in FPGAs, while often yielding different performance, often results in the same logical functionality. Further, running a design at speed on an FPGA prototype with real stimulus allows for a far more exhaustive and realistic functional coverage as well as early integration with embedded software. Thus FPGA prototyping can be used effectively to supplement and extend existing functional verification methodologies.
As ASIC designs have grown larger at a much faster pace than FPGA devices, often multiple FPGA devices must be used to prototype a single ASIC. The obstacle of using multiple devices is the task of connecting all of the logical blocks of the ASIC design across multiple FPGA devices. Physically, with the use of the high speed I/O blocks in FPGA devices, connectivity between physical devices has been simplified. However, methods for logically connecting the design blocks have proven to be manually intensive and error prone. With the introduction of SystemVerilog, an evolutionary RTL language, and advanced mixed language synthesis tools such as Mentor Graphics' Precision Synthesis, the procedure for connection has also been simplified.
ASICs provide a solution for capturing high performance complex design concepts and preventing competitors from simply implementing comparable designs.
However, creating an ASIC is a high-investment proposition with development costs approaching $20M for a 90 nm ASIC/SoC design and expected to top $40M for a 45 nm SoC. Thus, increasingly, only a high-volume product can afford an ASIC.
Besides the increase in mask-set cost, total development cost is also increasing due to the reduced probability of getting the design right the first time. As design complexity continues to increase, surveys have shown that only about a third of today's SoC designs are bug-free in first silicon, and nearly half of all respins are reported as being caused by functional logic error(s). As a result, verification managers are now exploring ways to strengthen their functional verification methodologies.
Before starting on a true ASIC design, to demonstrate that concepts are sound and that designs can be implemented, a lower-cost method of using FPGAs to prototype ASIC designs as part of an ASIC verification methodology has been growing in popularity.
Prototyping ASIC designs in FPGAs, while often yielding different performance, often results in the same logical functionality. Further, running a design at speed on an FPGA prototype with real stimulus allows for a far more exhaustive and realistic functional coverage as well as early integration with embedded software. Thus FPGA prototyping can be used effectively to supplement and extend existing functional verification methodologies.
As ASIC designs have grown larger at a much faster pace than FPGA devices, often multiple FPGA devices must be used to prototype a single ASIC. The obstacle of using multiple devices is the task of connecting all of the logical blocks of the ASIC design across multiple FPGA devices. Physically, with the use of the high speed I/O blocks in FPGA devices, connectivity between physical devices has been simplified. However, methods for logically connecting the design blocks have proven to be manually intensive and error prone. With the introduction of SystemVerilog, an evolutionary RTL language, and advanced mixed language synthesis tools such as Mentor Graphics' Precision Synthesis, the procedure for connection has also been simplified.
Taking a closer look at Intel's Atom multicore processor architecture
Multi-core processors are everywhere. In desktop computing, it is almost impossible to buy a computer today that doesn't have a multi-core CPU inside. Multi-core technology is also having an impact in the embedded space, where increased performance per Watt presents a compelling case for migration.
Developers are increasingly turning to multi-core because they either want to improve the processing power of their product, or they want to take advantage of some other technology that is 'bundled' within with the multi-core package. Because this new parallel world can also represent an engineering challenge, this article offers seven tips to help ease those first steps towards using these devices.
It's not unnatural to want to use the latest technology in our favourite embedded design. It is tempting to make a design a technological showcase, using all the latest knobs, bells and whistles. However, it is worth reminding ourselves that what is fashion today will be 'old hat' within a relatively short period. If you have an application that works well the way it is, and is likely to keep performing adequately within the lifetime of the product, then maybe there is no point in upgrading.
One of the benefits of recent trends within processor design has been the focus on power efficiency. Prior to the introduction of multi-core, new performance barriers were reached by providing silicon that could run at ever higher clock speeds. An unfortunate by-product of this speed race was that the heat dissipated from such devices made them unsuitable for many embedded applications.
As clock speeds increased, the limits of the transistor technology physics were moving ever closer. Researchers looked for new ways to increase performance without further increasing power consumption. It was discovered that by turning down the clock speeds and then adding additional cores to a processor, it was possible to get a much improved performance per Watt measurement.
The introduction of multi-core, along with new gate technologies and a redesign of the most power-hungry parts of a CPU, has led to processors that use significantly less power, yet deliver greater raw processing performance than their antecedents.
An example is the Intel Atom, a low power IA processor which uses 45nm Hi-K transistor gates. By implementing an in-order pipeline, adding additional deep sleep states, supporting SIMD (Single Instruction Multiple Data) instructions and using efficient instruction decoding and scheduling, Intel has produced a powerful but not power-hungry piece of silicon. Taking advantage of the lower power envelope could in itself be a valid reason for using multi-core devices in an embedded design " even if the target application is still single-threaded.
Multi-core processors are everywhere. In desktop computing, it is almost impossible to buy a computer today that doesn't have a multi-core CPU inside. Multi-core technology is also having an impact in the embedded space, where increased performance per Watt presents a compelling case for migration.
Developers are increasingly turning to multi-core because they either want to improve the processing power of their product, or they want to take advantage of some other technology that is 'bundled' within with the multi-core package. Because this new parallel world can also represent an engineering challenge, this article offers seven tips to help ease those first steps towards using these devices.
It's not unnatural to want to use the latest technology in our favourite embedded design. It is tempting to make a design a technological showcase, using all the latest knobs, bells and whistles. However, it is worth reminding ourselves that what is fashion today will be 'old hat' within a relatively short period. If you have an application that works well the way it is, and is likely to keep performing adequately within the lifetime of the product, then maybe there is no point in upgrading.
One of the benefits of recent trends within processor design has been the focus on power efficiency. Prior to the introduction of multi-core, new performance barriers were reached by providing silicon that could run at ever higher clock speeds. An unfortunate by-product of this speed race was that the heat dissipated from such devices made them unsuitable for many embedded applications.
As clock speeds increased, the limits of the transistor technology physics were moving ever closer. Researchers looked for new ways to increase performance without further increasing power consumption. It was discovered that by turning down the clock speeds and then adding additional cores to a processor, it was possible to get a much improved performance per Watt measurement.
The introduction of multi-core, along with new gate technologies and a redesign of the most power-hungry parts of a CPU, has led to processors that use significantly less power, yet deliver greater raw processing performance than their antecedents.
An example is the Intel Atom, a low power IA processor which uses 45nm Hi-K transistor gates. By implementing an in-order pipeline, adding additional deep sleep states, supporting SIMD (Single Instruction Multiple Data) instructions and using efficient instruction decoding and scheduling, Intel has produced a powerful but not power-hungry piece of silicon. Taking advantage of the lower power envelope could in itself be a valid reason for using multi-core devices in an embedded design " even if the target application is still single-threaded.
Use advanced architectural extensions
All the latest generation of CPUs have various architectural extensions that are there for 'free' and should be taken advantage of. One very effective but often underused extension is support for SIMD - that is, doing several calculations in one instruction.
Often developers ignore these advanced operations because of the perceived effort of adding such instructions to application code. While it is possible to use these instructions by adding macros, inline assembler or dedicated library functions to the application code, a favourite of many developers is to rely on the compiler to automatically insert such instruction in the generated code.
One technique known as 'auto-vectorisation' can lead to a significant performance boost of an application. In this technique the compiler looks for calculations that are performed in a loop. By replacing such calculations with, say, Streaming SIMD Extension (SSE) instructions, the compiler effectively reduces the number of loop iterations required. Some developers have seen their applications run twice as fast by turning on auto-vectorisation in the compiler.
Like the power gains of the previous section, using these architectural extensions may be a valid reason in itself for using a multi-core processor, even if you are not developing threaded code.
Not all programs are good candidates for parallelism. Even if your program seems to need a 'parallel facelift', it does not necessarily follow that going multi-core will help you. For example, say your product is an application running real-time weather pattern simulations, based on data collected from a number of remote sensors.
The measurements of wind speed, direction, temperature and humidity are being used to calculate the weather pattern over the next 30 minutes. Imagine that the application always produces its calculation results too late, and the longer the application runs the worse the timeliness of the simulation is.
One could assume that the poor performance is because the CPU is not powerful enough to do the calculations in time. Going parallel might be the right solution " but how do we prove this? Of course, it could be that the real bottleneck is an IO problem, the reason for the poor application performance being the implementation of the remote data collection and not excessive CPU load.
<>There are a number of profiling tools available that can help form a correct picture of the running program. Such analysers typically rely on runtime architectural events that are generated by the CPU. Before you migrate your application to multi-core, it would be worth analysing the application with such a tool, using the information you glean to help in the decision making process.
There are different ways that one can introduce parallelism into the high-level design of a program. Three common strategies available are functional parallelism, data parallelism and software pipe-lining.In functional parallelism, each task or thread is allocated a distinct job; for example one thread might be reading a temperature transducer, while another thread is carrying out a series of CPU intensive calculations.
In data parallelism, each task or thread carries out the same type of activity. For example, a large matrix multiplication can be shared between, say, four cores, thus reducing the time taken to perform that calculation by a factor of four.
A software pipeline is somewhat akin to a production line, where a series of workers carry out a specific duty before passing the work onto the next worker in the production line. In a multi-core environment, each worker " or pipeline " is assigned to a different core. In traditional parallel programming, much emphasis is laid on the scalability of an application. Good scalability implies that a program running on a dual-core processor would run twice as fast on a quad-core.
In embedded systems, computing scalability is less important because the execution of the end product tends not to be changed; the shelf-life of the end product usually being measured in years rather than months. It may be that when moving to multi-core, the embedded engineer should not be over-sensitive to the scalability of his design, but rather use a combination of data and functional parallelism that delivers the best performance.
Using high-level constructs
Threading is not a new discipline and most operating systems have an API that allows the programmer to create and manage threads. Using the APIs directly in the code is quite tough, so the recommendation is to use a higher level of abstraction. One way of implementing threading is to use various high-level constructs or extensions to the programming language.
OpenMP is a pragma-based language extension for C/C++ and FORTRAN that allows the programmer to very easily introduce parallelism into an existing program. The standard has been adopted by a number of compiler vendors including GNU, Intel, and Microsoft.
A full description of the standard can be found at www.openmp.org With OpenMP it is easy to incrementally add parallelism to a program. Because the programming is pragma based, your code can still be built on compilers that don't support OpenMP " the compiler in this case would just issue a warning that it has found an unsupported pragma.
As stated earlier, functional parallelism is potentially more interesting than data parallelism when developing an embedded application. An alternative to using OpenMP is to use one of the newly emerging language extensions which supply similar functionality. It is expected that eventually such language extensions will be adopted by an appropriate standards committee. An experimental compiler with such extensions can be found at www.whatif.intel.com.
Another approach to traditional programming languages is to use a graphical development environment. There are a number of 'program by drawing' development tools that take care of all the low level threading implementation for the developer.
One example is National Instruments' LabVIEW, which allows the programmer to design his program diagrammatically, by connecting a number of objects together. Support for multi-core is simply adding a loop block to the diagram.
When programs run in parallel, they can be very difficult to debug " especially when using tools that are not enabled for parallelism. Identifying and debugging issues related to using shared resources and shared variables, synchronisation between different threads and dealing with deadlocks and livelocks are notoriously difficult.
However, there is a now a growing number of tools available from different vendors, specifically designed to aid debugging and tuning of parallel applications. The Intel Thread Checker and Intel Thread Profiler are examples of tools that can be can be used to debug and tune parallel programs
Where no parallel debugging tools are available for the embedded target you are working on, it is a legitimate practice to use standard desktop tools, carrying out the first set of tests on a desktop rather than the embedded target. It's a common experience that threading issues appearing on the target can often be first captured by running the application code on a desktop machine.
Stephen Blair-Chappell is a Technical Consulting Engineer at Intel Compiler Labs.
Developers are increasingly turning to multi-core because they either want to improve the processing power of their product, or they want to take advantage of some other technology that is 'bundled' within with the multi-core package. Because this new parallel world can also represent an engineering challenge, this article offers seven tips to help ease those first steps towards using these devices.
It's not unnatural to want to use the latest technology in our favourite embedded design. It is tempting to make a design a technological showcase, using all the latest knobs, bells and whistles. However, it is worth reminding ourselves that what is fashion today will be 'old hat' within a relatively short period. If you have an application that works well the way it is, and is likely to keep performing adequately within the lifetime of the product, then maybe there is no point in upgrading.
One of the benefits of recent trends within processor design has been the focus on power efficiency. Prior to the introduction of multi-core, new performance barriers were reached by providing silicon that could run at ever higher clock speeds. An unfortunate by-product of this speed race was that the heat dissipated from such devices made them unsuitable for many embedded applications.
As clock speeds increased, the limits of the transistor technology physics were moving ever closer. Researchers looked for new ways to increase performance without further increasing power consumption. It was discovered that by turning down the clock speeds and then adding additional cores to a processor, it was possible to get a much improved performance per Watt measurement.
The introduction of multi-core, along with new gate technologies and a redesign of the most power-hungry parts of a CPU, has led to processors that use significantly less power, yet deliver greater raw processing performance than their antecedents.
An example is the Intel Atom, a low power IA processor which uses 45nm Hi-K transistor gates. By implementing an in-order pipeline, adding additional deep sleep states, supporting SIMD (Single Instruction Multiple Data) instructions and using efficient instruction decoding and scheduling, Intel has produced a powerful but not power-hungry piece of silicon. Taking advantage of the lower power envelope could in itself be a valid reason for using multi-core devices in an embedded design " even if the target application is still single-threaded.
Multi-core processors are everywhere. In desktop computing, it is almost impossible to buy a computer today that doesn't have a multi-core CPU inside. Multi-core technology is also having an impact in the embedded space, where increased performance per Watt presents a compelling case for migration.
Developers are increasingly turning to multi-core because they either want to improve the processing power of their product, or they want to take advantage of some other technology that is 'bundled' within with the multi-core package. Because this new parallel world can also represent an engineering challenge, this article offers seven tips to help ease those first steps towards using these devices.
It's not unnatural to want to use the latest technology in our favourite embedded design. It is tempting to make a design a technological showcase, using all the latest knobs, bells and whistles. However, it is worth reminding ourselves that what is fashion today will be 'old hat' within a relatively short period. If you have an application that works well the way it is, and is likely to keep performing adequately within the lifetime of the product, then maybe there is no point in upgrading.
One of the benefits of recent trends within processor design has been the focus on power efficiency. Prior to the introduction of multi-core, new performance barriers were reached by providing silicon that could run at ever higher clock speeds. An unfortunate by-product of this speed race was that the heat dissipated from such devices made them unsuitable for many embedded applications.
As clock speeds increased, the limits of the transistor technology physics were moving ever closer. Researchers looked for new ways to increase performance without further increasing power consumption. It was discovered that by turning down the clock speeds and then adding additional cores to a processor, it was possible to get a much improved performance per Watt measurement.
The introduction of multi-core, along with new gate technologies and a redesign of the most power-hungry parts of a CPU, has led to processors that use significantly less power, yet deliver greater raw processing performance than their antecedents.
An example is the Intel Atom, a low power IA processor which uses 45nm Hi-K transistor gates. By implementing an in-order pipeline, adding additional deep sleep states, supporting SIMD (Single Instruction Multiple Data) instructions and using efficient instruction decoding and scheduling, Intel has produced a powerful but not power-hungry piece of silicon. Taking advantage of the lower power envelope could in itself be a valid reason for using multi-core devices in an embedded design " even if the target application is still single-threaded.
Use advanced architectural extensions
All the latest generation of CPUs have various architectural extensions that are there for 'free' and should be taken advantage of. One very effective but often underused extension is support for SIMD - that is, doing several calculations in one instruction.
Often developers ignore these advanced operations because of the perceived effort of adding such instructions to application code. While it is possible to use these instructions by adding macros, inline assembler or dedicated library functions to the application code, a favourite of many developers is to rely on the compiler to automatically insert such instruction in the generated code.
One technique known as 'auto-vectorisation' can lead to a significant performance boost of an application. In this technique the compiler looks for calculations that are performed in a loop. By replacing such calculations with, say, Streaming SIMD Extension (SSE) instructions, the compiler effectively reduces the number of loop iterations required. Some developers have seen their applications run twice as fast by turning on auto-vectorisation in the compiler.
Like the power gains of the previous section, using these architectural extensions may be a valid reason in itself for using a multi-core processor, even if you are not developing threaded code.
Not all programs are good candidates for parallelism. Even if your program seems to need a 'parallel facelift', it does not necessarily follow that going multi-core will help you. For example, say your product is an application running real-time weather pattern simulations, based on data collected from a number of remote sensors.
The measurements of wind speed, direction, temperature and humidity are being used to calculate the weather pattern over the next 30 minutes. Imagine that the application always produces its calculation results too late, and the longer the application runs the worse the timeliness of the simulation is.
One could assume that the poor performance is because the CPU is not powerful enough to do the calculations in time. Going parallel might be the right solution " but how do we prove this? Of course, it could be that the real bottleneck is an IO problem, the reason for the poor application performance being the implementation of the remote data collection and not excessive CPU load.
<>There are a number of profiling tools available that can help form a correct picture of the running program. Such analysers typically rely on runtime architectural events that are generated by the CPU. Before you migrate your application to multi-core, it would be worth analysing the application with such a tool, using the information you glean to help in the decision making process.
There are different ways that one can introduce parallelism into the high-level design of a program. Three common strategies available are functional parallelism, data parallelism and software pipe-lining.In functional parallelism, each task or thread is allocated a distinct job; for example one thread might be reading a temperature transducer, while another thread is carrying out a series of CPU intensive calculations.
In data parallelism, each task or thread carries out the same type of activity. For example, a large matrix multiplication can be shared between, say, four cores, thus reducing the time taken to perform that calculation by a factor of four.
A software pipeline is somewhat akin to a production line, where a series of workers carry out a specific duty before passing the work onto the next worker in the production line. In a multi-core environment, each worker " or pipeline " is assigned to a different core. In traditional parallel programming, much emphasis is laid on the scalability of an application. Good scalability implies that a program running on a dual-core processor would run twice as fast on a quad-core.
In embedded systems, computing scalability is less important because the execution of the end product tends not to be changed; the shelf-life of the end product usually being measured in years rather than months. It may be that when moving to multi-core, the embedded engineer should not be over-sensitive to the scalability of his design, but rather use a combination of data and functional parallelism that delivers the best performance.
Using high-level constructs
Threading is not a new discipline and most operating systems have an API that allows the programmer to create and manage threads. Using the APIs directly in the code is quite tough, so the recommendation is to use a higher level of abstraction. One way of implementing threading is to use various high-level constructs or extensions to the programming language.
OpenMP is a pragma-based language extension for C/C++ and FORTRAN that allows the programmer to very easily introduce parallelism into an existing program. The standard has been adopted by a number of compiler vendors including GNU, Intel, and Microsoft.
A full description of the standard can be found at www.openmp.org With OpenMP it is easy to incrementally add parallelism to a program. Because the programming is pragma based, your code can still be built on compilers that don't support OpenMP " the compiler in this case would just issue a warning that it has found an unsupported pragma.
As stated earlier, functional parallelism is potentially more interesting than data parallelism when developing an embedded application. An alternative to using OpenMP is to use one of the newly emerging language extensions which supply similar functionality. It is expected that eventually such language extensions will be adopted by an appropriate standards committee. An experimental compiler with such extensions can be found at www.whatif.intel.com.
Another approach to traditional programming languages is to use a graphical development environment. There are a number of 'program by drawing' development tools that take care of all the low level threading implementation for the developer.
One example is National Instruments' LabVIEW, which allows the programmer to design his program diagrammatically, by connecting a number of objects together. Support for multi-core is simply adding a loop block to the diagram.
When programs run in parallel, they can be very difficult to debug " especially when using tools that are not enabled for parallelism. Identifying and debugging issues related to using shared resources and shared variables, synchronisation between different threads and dealing with deadlocks and livelocks are notoriously difficult.
However, there is a now a growing number of tools available from different vendors, specifically designed to aid debugging and tuning of parallel applications. The Intel Thread Checker and Intel Thread Profiler are examples of tools that can be can be used to debug and tune parallel programs
Where no parallel debugging tools are available for the embedded target you are working on, it is a legitimate practice to use standard desktop tools, carrying out the first set of tests on a desktop rather than the embedded target. It's a common experience that threading issues appearing on the target can often be first captured by running the application code on a desktop machine.
Stephen Blair-Chappell is a Technical Consulting Engineer at Intel Compiler Labs.
XPort®
Build Serial to Ethernet Connectivity and Control into Your Products, Quickly and Simply
XPort® is a compact, integrated solution to web enable virtually any device with serial capability. By incorporating XPort to a product design, manufacturers can quickly and easily offer serial to Ethernet networking capability as a standard feature — so they can be accessed and controlled over the Internet.
Full Networking in a Tiny Package
XPort embedded device server removes the complexity – of designing network connectivity into a product by incorporating all of the required hardware and software inside a single embedded Ethernet solution. Smaller than your thumb, it includes all essential networking features, including a 10Base- T/100Base-TX Ethernet connection, proven operating system, an embedded web server, e-mail alerts, a full TCP/IP protocol stack, and 256-bit AES encryption for secure communications. This easy-to-embed networking processor module enables engineers to focus on their core competency while reducing development time and cost and increasing product value.
Integrated Network Communications Module
XPort is powered by our DSTni™ network processor SoC, which includes a 10/100 MAC/PHY and 256 KB of SRAM. It features a built-in web server for communications with a device via a standard Internet browser. Web capability can be used for remote configuration, real-time monitoring or troubleshooting. XPort has 512 KB of onmodule Flash for web pages and software upgrades. It acts as a dedicated co-processor that optimizes network activities permitting the host microprocessor to function at maximum efficiency.
Building Intelligent Devices
With XPort you can embed intelligence into any electronic product for applications such as:
Remote diagnostics and upgrades
Asset tracking and replenishment
Automation and control
Power management
Remote collaboration
Personalized content delivery
Robust, Feature-Rich Software Suite
Eliminating the need to negotiate the intricacies of Transmission Control Protocol (TCP) or Internet Protocol (IP), XPort incorporates:
Robust Real Time Operating System (RTOS)
Full-featured network protocol stack
Proven, ready-to-use serial-to-wireless application
Built-in web server for device communication and configuration via a standard browser
The Windows-based DeviceInstaller™ makes configuring one or more XPorts in a subnet quick and easy.
Install and configure XPort and load firmware
Assign IP & other network specific addresses
Set wireless parameters
Load custom web pages and view specific device data
Enable web-based configuration of the device
Ping or query the attached device(s) over the network
Allow Telnet communication with the device(s)
Order Information & Part Numbers
Lantronix products are available from a wide variety of leading technology vendors.
Click here to use our Partner Locator.
To speak with a Lantronix sales representative in North America, call +1 (800) 526-8764. For a full listing of Lantronix worldwide offices, please see our Contact Information page.
Model Part Number Description
XPort XE
(Min. Quantity 50 units) XP1001000-03R XPort RoHS Extended Temperature
RoHS Cert. of Compliance
XP1001001-03R XPort RoHS Commercial Temperature
RoHS Cert. of Compliance
XP1001000M-03R XPort XE RoHS Extended Temperature, with MODBUS
RoHS Cert. of Compliance
XPort SE
(Min. Quantity 50 units) XP1002000-03R XPort RoHS Extended Temperature, with Encryption
RoHS Cert. of Compliance
XP1002001-03R XPort RoHS Commercial Temperature, with Encryption
RoHS Cert. of Compliance
XPort SMPL XP100200S-03R XPort RoHS Extended Temperature, with Encryption
- Sample
RoHS Cert. of Compliance
XPort 485
(Min. Quantity 50 units) XP1004000-03R XPort RS-485 RoHS Extended Temperature, with Encryption
XPort 485 SMPL XP100400S-03R XPort RS-485 RoHS Extended Temperature, with Encryption - Sample
XPort Evaluation Kit XP100200K-03 XPort Evaluation Kit
(More Information)
Features & Specifications
Serial Interface
Interface CMOS (Asynchronous, 5V Tolerant)
Data Rates 300 bps to 921,600 bps
Characters 7 or 8 data bits
Parity odd, even, none
Stop Bits 1 or 2
Control Signals DTR/DCD, CTS, RTS
Flow Control XON/XOFF, RTS/CTS
Programmable I/O 3 PIO pins (software selectable)
Network Interface
Interface Ethernet 10Base-T or 100Base-TX (Auto-Sensing)
Connector RJ45
Protocols TCP/IP, UDP/IP, ARP, ICMP, SNMP, TFTP, Telnet, DHCP, BOOTP, HTTP, and AutoIP
Indicators (LED)
10Base-T connection
100Base-TX connection
Link & activity indicator - Full/half duplex
Management
SNMP, Telnet, serial, internal web server, and Microsoft Windows®-based utility for configuration
Security
Password protection
Optional 256-bit AES Rijndael encryption
Internal Web Server
Storage Capacity 384KB for web pages
Architecture
CPU Based on the DSTni-EX enhanced 16-bit, 48MHz or 88MHz, x86 architecture
Memory 256KB SRAM and 512KB flash
Firmware Upgradeable via TFTP and serially
Power
Input Voltage 3.3 VDC
Environmental
Extended Temp -40° to 85°C (-40° to 185°F)
Commercial Temp 0° to 70°C (32° to 158°F)
Storage -40° to 85°C (-40° to 185°F)
Packaging
Dimensions 33.9 x 16.25 x 13.5mm (1.33 x 0.64 x 0.53 in)
Weight 9.6 g (0.34 oz)
Included Software
Web manager, Windows®-based DeviceInstaller configuration software and Com Port Redirector.
XPort® is a compact, integrated solution to web enable virtually any device with serial capability. By incorporating XPort to a product design, manufacturers can quickly and easily offer serial to Ethernet networking capability as a standard feature — so they can be accessed and controlled over the Internet.
Full Networking in a Tiny Package
XPort embedded device server removes the complexity – of designing network connectivity into a product by incorporating all of the required hardware and software inside a single embedded Ethernet solution. Smaller than your thumb, it includes all essential networking features, including a 10Base- T/100Base-TX Ethernet connection, proven operating system, an embedded web server, e-mail alerts, a full TCP/IP protocol stack, and 256-bit AES encryption for secure communications. This easy-to-embed networking processor module enables engineers to focus on their core competency while reducing development time and cost and increasing product value.
Integrated Network Communications Module
XPort is powered by our DSTni™ network processor SoC, which includes a 10/100 MAC/PHY and 256 KB of SRAM. It features a built-in web server for communications with a device via a standard Internet browser. Web capability can be used for remote configuration, real-time monitoring or troubleshooting. XPort has 512 KB of onmodule Flash for web pages and software upgrades. It acts as a dedicated co-processor that optimizes network activities permitting the host microprocessor to function at maximum efficiency.
Building Intelligent Devices
With XPort you can embed intelligence into any electronic product for applications such as:
Remote diagnostics and upgrades
Asset tracking and replenishment
Automation and control
Power management
Remote collaboration
Personalized content delivery
Robust, Feature-Rich Software Suite
Eliminating the need to negotiate the intricacies of Transmission Control Protocol (TCP) or Internet Protocol (IP), XPort incorporates:
Robust Real Time Operating System (RTOS)
Full-featured network protocol stack
Proven, ready-to-use serial-to-wireless application
Built-in web server for device communication and configuration via a standard browser
The Windows-based DeviceInstaller™ makes configuring one or more XPorts in a subnet quick and easy.
Install and configure XPort and load firmware
Assign IP & other network specific addresses
Set wireless parameters
Load custom web pages and view specific device data
Enable web-based configuration of the device
Ping or query the attached device(s) over the network
Allow Telnet communication with the device(s)
Order Information & Part Numbers
Lantronix products are available from a wide variety of leading technology vendors.
Click here to use our Partner Locator.
To speak with a Lantronix sales representative in North America, call +1 (800) 526-8764. For a full listing of Lantronix worldwide offices, please see our Contact Information page.
Model Part Number Description
XPort XE
(Min. Quantity 50 units) XP1001000-03R XPort RoHS Extended Temperature
RoHS Cert. of Compliance
XP1001001-03R XPort RoHS Commercial Temperature
RoHS Cert. of Compliance
XP1001000M-03R XPort XE RoHS Extended Temperature, with MODBUS
RoHS Cert. of Compliance
XPort SE
(Min. Quantity 50 units) XP1002000-03R XPort RoHS Extended Temperature, with Encryption
RoHS Cert. of Compliance
XP1002001-03R XPort RoHS Commercial Temperature, with Encryption
RoHS Cert. of Compliance
XPort SMPL XP100200S-03R XPort RoHS Extended Temperature, with Encryption
- Sample
RoHS Cert. of Compliance
XPort 485
(Min. Quantity 50 units) XP1004000-03R XPort RS-485 RoHS Extended Temperature, with Encryption
XPort 485 SMPL XP100400S-03R XPort RS-485 RoHS Extended Temperature, with Encryption - Sample
XPort Evaluation Kit XP100200K-03 XPort Evaluation Kit
(More Information)
Features & Specifications
Serial Interface
Interface CMOS (Asynchronous, 5V Tolerant)
Data Rates 300 bps to 921,600 bps
Characters 7 or 8 data bits
Parity odd, even, none
Stop Bits 1 or 2
Control Signals DTR/DCD, CTS, RTS
Flow Control XON/XOFF, RTS/CTS
Programmable I/O 3 PIO pins (software selectable)
Network Interface
Interface Ethernet 10Base-T or 100Base-TX (Auto-Sensing)
Connector RJ45
Protocols TCP/IP, UDP/IP, ARP, ICMP, SNMP, TFTP, Telnet, DHCP, BOOTP, HTTP, and AutoIP
Indicators (LED)
10Base-T connection
100Base-TX connection
Link & activity indicator - Full/half duplex
Management
SNMP, Telnet, serial, internal web server, and Microsoft Windows®-based utility for configuration
Security
Password protection
Optional 256-bit AES Rijndael encryption
Internal Web Server
Storage Capacity 384KB for web pages
Architecture
CPU Based on the DSTni-EX enhanced 16-bit, 48MHz or 88MHz, x86 architecture
Memory 256KB SRAM and 512KB flash
Firmware Upgradeable via TFTP and serially
Power
Input Voltage 3.3 VDC
Environmental
Extended Temp -40° to 85°C (-40° to 185°F)
Commercial Temp 0° to 70°C (32° to 158°F)
Storage -40° to 85°C (-40° to 185°F)
Packaging
Dimensions 33.9 x 16.25 x 13.5mm (1.33 x 0.64 x 0.53 in)
Weight 9.6 g (0.34 oz)
Included Software
Web manager, Windows®-based DeviceInstaller configuration software and Com Port Redirector.
WiPort®
Build Embedded 802.11 b/g Wireless Networking Into Your Products!
A compact, integrated hardware and software module, WiPort® enables you to build wireless networking into virtually any electronic device with serial or Ethernet capability. With WiPort your products can be wirelessly accessed and controlled over a network or the Internet!
The matchbook-sized WiPort takes the complexity out of RF design and embedded Ethernet networking and WiPort enables engineers to focus on their core competency of designing products. It minimizes engineering risk, reduces cost and shortens development time. Just apply power and UART output, and the product is wireless and network-ready!
Complete Wireless Network Processing Module
Powered by a Lantronix DSTni™ Ethernet processor SoC that includes a 10Base-T/100Base-TX MAC/PHY and 256 KB of on-chip SRAM, WiPort also includes a complete 802.11 b/g radio and 2MB of Flash memory for web page storage and system upgrades. WiPort is a dedicated co-processor module that optimizes network activity, permitting the device’s host microprocessor to function at maximum efficiency. WiPort connects through its coaxial “pigtail” to an external panel-mounted antenna for rapid electromechanical integration. WiPort works with serial or Ethernet interface devices. SPI, I2C, USB or CAN connectivity can be enabled as a future option.
Bulletproof Security
With IEEE 802.11i-PSK or WPA (PSK, TKIP) encryption WiPort offers heightened security. WiPort also supports 256-bit Advanced Encryption Standards (Rjindael) encryption for true end-to-end (wired to wireless to wired) secure data transfer.
Robust, Feature-Rich Software Suite
Eliminating the need to negotiate the intricacies of Transmission Control Protocol (TCP) or Internet Protocol (IP), WiPort incorporates:
Robust Real Time Operating System (RTOS)
Full-featured network protocol stack
Proven, ready-to-use serial-to-wireless application
Built-in web server for device communication and configuration via a standard browser
The Windows-based DeviceInstaller™ makes configuring one or more WiPorts in a subnet quick and easy.
Install and configure WiPort and load firmware
Assign IP & other network specific addresses
Set wireless parameters
Load custom web pages and view specific device data
Enable web-based configuration of the device
Ping or query the attached device(s) over the network
Allow Telnet communication with the device(s)
FCC Certified for Immediate Deployment
WiPort is certified by the U.S. Federal Communications Commission (FCC). This allows you to leverage the Lantronix WiPort FCC license grant to your label and bypass 802.11 regulatory testing. This accelerates time-to-market and reduces development and testing costs. WiPort is also pre-tested for European telecommunications regulations.
Ethernet-to-Wireless Bridging
With a separate Ethernet port, WiPort offers the unique ability to transparently bridge existing Ethernet-ready devices to a wireless network.
Scan, Gather and Report Radio Parameters
With its Scan command, WiPort enables the ability to report MAC address, RSSI and SSID which are extremely useful during site survey work. The Network Status command additionally reports channel, infra/adhoc, security type, authentication, negotiated encryption types for the current association.
A compact, integrated hardware and software module, WiPort® enables you to build wireless networking into virtually any electronic device with serial or Ethernet capability. With WiPort your products can be wirelessly accessed and controlled over a network or the Internet!
The matchbook-sized WiPort takes the complexity out of RF design and embedded Ethernet networking and WiPort enables engineers to focus on their core competency of designing products. It minimizes engineering risk, reduces cost and shortens development time. Just apply power and UART output, and the product is wireless and network-ready!
Complete Wireless Network Processing Module
Powered by a Lantronix DSTni™ Ethernet processor SoC that includes a 10Base-T/100Base-TX MAC/PHY and 256 KB of on-chip SRAM, WiPort also includes a complete 802.11 b/g radio and 2MB of Flash memory for web page storage and system upgrades. WiPort is a dedicated co-processor module that optimizes network activity, permitting the device’s host microprocessor to function at maximum efficiency. WiPort connects through its coaxial “pigtail” to an external panel-mounted antenna for rapid electromechanical integration. WiPort works with serial or Ethernet interface devices. SPI, I2C, USB or CAN connectivity can be enabled as a future option.
Bulletproof Security
With IEEE 802.11i-PSK or WPA (PSK, TKIP) encryption WiPort offers heightened security. WiPort also supports 256-bit Advanced Encryption Standards (Rjindael) encryption for true end-to-end (wired to wireless to wired) secure data transfer.
Robust, Feature-Rich Software Suite
Eliminating the need to negotiate the intricacies of Transmission Control Protocol (TCP) or Internet Protocol (IP), WiPort incorporates:
Robust Real Time Operating System (RTOS)
Full-featured network protocol stack
Proven, ready-to-use serial-to-wireless application
Built-in web server for device communication and configuration via a standard browser
The Windows-based DeviceInstaller™ makes configuring one or more WiPorts in a subnet quick and easy.
Install and configure WiPort and load firmware
Assign IP & other network specific addresses
Set wireless parameters
Load custom web pages and view specific device data
Enable web-based configuration of the device
Ping or query the attached device(s) over the network
Allow Telnet communication with the device(s)
FCC Certified for Immediate Deployment
WiPort is certified by the U.S. Federal Communications Commission (FCC). This allows you to leverage the Lantronix WiPort FCC license grant to your label and bypass 802.11 regulatory testing. This accelerates time-to-market and reduces development and testing costs. WiPort is also pre-tested for European telecommunications regulations.
Ethernet-to-Wireless Bridging
With a separate Ethernet port, WiPort offers the unique ability to transparently bridge existing Ethernet-ready devices to a wireless network.
Scan, Gather and Report Radio Parameters
With its Scan command, WiPort enables the ability to report MAC address, RSSI and SSID which are extremely useful during site survey work. The Network Status command additionally reports channel, infra/adhoc, security type, authentication, negotiated encryption types for the current association.
IP and Ethernet Interfaces
There is a general consensus that in years to come more and more Internet devices will be embedded and not PC oriented. Just one such prediction is that by 2010, 95% of Internet-connected devices will not be computers. So if they are not computers, what will they be? Embedded Internet devices.
One popular solution is to use an 8 bit microcontroller such as a Rabbit 2000, AVR or PIC and a Ethernet MAC such as a CS8900A or RTL8029AS hanging of it’s parallel port pins in 8 bit mode. A TCP/IP stack is normally written in C and can be striped of features and ported to these resource limited microcontrollers. While this works and we detail many such boards below, a little debate is brewing over it’s reliability and functionality.
With DOS (denial of service) attacks becoming more and more common, it doesn’t take much to knock your little 8 bit microcontroller off the network. In fact some configurations have a little trouble keeping up with the high volume of broadcast packets floating around a loaded network, let alone any malicious attacks.
One solution of course is to put in a bigger processor. This is the case with Embedded Linux devices such as Coldfire, DragonBall or ARM based devices. They are quite powerful enough to allow a suitable bandwidth and not be susceptible to someone’s malicious intent.
The other solution is to use a hardware TCP/IP stack. A hardware based stack is not new. If you have followed this site, you will be aware of the Sekio S-7600A hardware stack which incorporated a TCP/IP stack with a PPP controller so you could connect it to a modem. Sekio had licensed the technology from Iready Corporation. While it had it’s place in data logging or dial on demand applications where your device could dial up the Internet and send you an email to the effect that your house has been broken into or the past 24 hours logged data etc, it wouldn't connect to the popular ethernet networks present everywhere today.
The next logical progression had to be the Ethernet interface. Sekio has exited the embedded Internet business discontinuing it’s S-7600 on the 1st September. However the concept is still alive.
A hardware TCP/IP stack has a couple of advantages. Firstly as they are hardware based, most run at close to line speeds encapsulating and striping streams of data on the fly. This makes it increasingly more difficult to cause a DOS attack and almost impossible to run malicious code using principals of buffer overruns etc. However being hardware makes it difficult to upgrade should little quirks be found allowing say SYN attacks for example.
Later we detail some devices from Ipsil and Connect One. Both have the ability to upload new firmware which future proofs the designs in these peripheral devices. However the Ipsil and Connect One devices on the market today rely on an external ethernet MAC such as the popular CS8900A or RTL8029AS. This contributes to the chip count.
Ipsil has preliminary data on their IPµ8932 which combines a webserver, Ethernet MAC layer, and TCP/IP controller all on a single chip. This allows the one chip with 20 digital or analog inputs to display webpages without the need of a microcontroller. Ipsil has WebHoles™ technology which allows holes (simular to server side includes principles) to be filled in with values from the I/O ports. If you do happen to need more complexity, you can add a microcontroller and talk via standard TCP/IP socket calls.
However WIZnet Inc already has a simular device on the Market. The W3150A incorporates a TCP/IP stack and a future proofed 10/100 Ethernet MAC. So when it comes to chip count, it makes sense to off load the burden of the TCP/IP stack into a second peripheral chip complete with Ethernet MAC. It can reduce time to market, as the design of the TCP/IP stack is omitted (or saves costs of licensing one), plus you have a more stable product. Your 8 bit micro effectively has more grunt now, as it's no longer responsible for the lower TCP/IP protocols and ethernet encapsulation. All these advantages and yet, still only two chips.
How long before the leading microcontroller manufacturers are going to integrate a hardware TCP/IP stack and ethernet MAC into their microcontrollers making a one chip solution?
Answer : WIZnet Inc. and Atmel Corporation to jointly develop and market Internet connectivity solutions.
WIZnet Inc. and Atmel Corporation has forged a strategic partnership to develop and co-market Internet connectivity solutions. As part of this agreement WIZnet will manufacture OEM products around Atmel’s AVR microcontrollers. Both have agreed to move in the direction of system-on-chip (SoC) which will see WIZnet’s TCP/IP hardwired technology be integrated with Atmel’s MCU cores. Outcome? An AVR with \ hardware TCP/IP stack and ethernet in the one chip. I can't wait. . . .
One popular solution is to use an 8 bit microcontroller such as a Rabbit 2000, AVR or PIC and a Ethernet MAC such as a CS8900A or RTL8029AS hanging of it’s parallel port pins in 8 bit mode. A TCP/IP stack is normally written in C and can be striped of features and ported to these resource limited microcontrollers. While this works and we detail many such boards below, a little debate is brewing over it’s reliability and functionality.
With DOS (denial of service) attacks becoming more and more common, it doesn’t take much to knock your little 8 bit microcontroller off the network. In fact some configurations have a little trouble keeping up with the high volume of broadcast packets floating around a loaded network, let alone any malicious attacks.
One solution of course is to put in a bigger processor. This is the case with Embedded Linux devices such as Coldfire, DragonBall or ARM based devices. They are quite powerful enough to allow a suitable bandwidth and not be susceptible to someone’s malicious intent.
The other solution is to use a hardware TCP/IP stack. A hardware based stack is not new. If you have followed this site, you will be aware of the Sekio S-7600A hardware stack which incorporated a TCP/IP stack with a PPP controller so you could connect it to a modem. Sekio had licensed the technology from Iready Corporation. While it had it’s place in data logging or dial on demand applications where your device could dial up the Internet and send you an email to the effect that your house has been broken into or the past 24 hours logged data etc, it wouldn't connect to the popular ethernet networks present everywhere today.
The next logical progression had to be the Ethernet interface. Sekio has exited the embedded Internet business discontinuing it’s S-7600 on the 1st September. However the concept is still alive.
A hardware TCP/IP stack has a couple of advantages. Firstly as they are hardware based, most run at close to line speeds encapsulating and striping streams of data on the fly. This makes it increasingly more difficult to cause a DOS attack and almost impossible to run malicious code using principals of buffer overruns etc. However being hardware makes it difficult to upgrade should little quirks be found allowing say SYN attacks for example.
Later we detail some devices from Ipsil and Connect One. Both have the ability to upload new firmware which future proofs the designs in these peripheral devices. However the Ipsil and Connect One devices on the market today rely on an external ethernet MAC such as the popular CS8900A or RTL8029AS. This contributes to the chip count.
Ipsil has preliminary data on their IPµ8932 which combines a webserver, Ethernet MAC layer, and TCP/IP controller all on a single chip. This allows the one chip with 20 digital or analog inputs to display webpages without the need of a microcontroller. Ipsil has WebHoles™ technology which allows holes (simular to server side includes principles) to be filled in with values from the I/O ports. If you do happen to need more complexity, you can add a microcontroller and talk via standard TCP/IP socket calls.
However WIZnet Inc already has a simular device on the Market. The W3150A incorporates a TCP/IP stack and a future proofed 10/100 Ethernet MAC. So when it comes to chip count, it makes sense to off load the burden of the TCP/IP stack into a second peripheral chip complete with Ethernet MAC. It can reduce time to market, as the design of the TCP/IP stack is omitted (or saves costs of licensing one), plus you have a more stable product. Your 8 bit micro effectively has more grunt now, as it's no longer responsible for the lower TCP/IP protocols and ethernet encapsulation. All these advantages and yet, still only two chips.
How long before the leading microcontroller manufacturers are going to integrate a hardware TCP/IP stack and ethernet MAC into their microcontrollers making a one chip solution?
Answer : WIZnet Inc. and Atmel Corporation to jointly develop and market Internet connectivity solutions.
WIZnet Inc. and Atmel Corporation has forged a strategic partnership to develop and co-market Internet connectivity solutions. As part of this agreement WIZnet will manufacture OEM products around Atmel’s AVR microcontrollers. Both have agreed to move in the direction of system-on-chip (SoC) which will see WIZnet’s TCP/IP hardwired technology be integrated with Atmel’s MCU cores. Outcome? An AVR with \ hardware TCP/IP stack and ethernet in the one chip. I can't wait. . . .
IP that works. Experience that Counts
CAST develops and supports over 100 different popular and standards-based IP cores, including 8051s, H.264, PCI Express, AES, and even complete platforms for ARM-based SoCs (see menu to the left).
With fifteen years of experience and hundreds of successful customers, we know how to deliver IP that works. Our complete, high-quality cores are ready for implementation in custom or structured ASICs or in FPGAs, and our world-wide team with a 24/7 culture provides quick, effective support.
Review datasheets and info for our 100+ cores here on our site, then contact your local sales office for more information.
IP Cores
From developing advanced new System on Chip (SoC) products to replacing obsolete parts, our broad range of proven IP cores has the functions and quality you need. We offer more cores independent of EDA tools and implementation technology than you'll find anywhere else, including:
8- and 16-bit processor compatibles for the Z80 and 68000; 32025 and 32025TX DSPs; and more successful 8051 variations and installations than anyone else.
Bus and network interfaces including Ethernet MACs, LIN, CAN, SPI, PCI and PCI Express.
The widest range of image compression cores available anywhere, from JPEG through JPEG 2000.
Security-ready AES, MD5, and SHA encryption cores.
Peripherals such as controllers for smart card readers and video displays.
An assortment of synchronous UARTs and an SDLC for communications.
A variety of basic logic parts and models.
A cost-effective solution for extending product life through 2901 processors, Z80 support functions, controllers, peripherals, and many more replacement parts.
All CAST IP cores come complete and ready to use, and are backed with our widely-regarded expert support.
SoC Kernel IP Platforms
Get a head start on your 32-bit processor based systems with our SoC Kernels and pre-integrated IP (PiP) platforms.
SOC Kernels are:
pre-integrated,
processor agnostic, and
technology independent.
They combine essential software like device drivers and boot code with multiple IP cores — timers, memory controllers, etc. — in a verified package ready for system development.
SOC Kernels are reasy to expand into more complex systems, and several pre-expanded PIPs are available now.
With fifteen years of experience and hundreds of successful customers, we know how to deliver IP that works. Our complete, high-quality cores are ready for implementation in custom or structured ASICs or in FPGAs, and our world-wide team with a 24/7 culture provides quick, effective support.
Review datasheets and info for our 100+ cores here on our site, then contact your local sales office for more information.
IP Cores
From developing advanced new System on Chip (SoC) products to replacing obsolete parts, our broad range of proven IP cores has the functions and quality you need. We offer more cores independent of EDA tools and implementation technology than you'll find anywhere else, including:
8- and 16-bit processor compatibles for the Z80 and 68000; 32025 and 32025TX DSPs; and more successful 8051 variations and installations than anyone else.
Bus and network interfaces including Ethernet MACs, LIN, CAN, SPI, PCI and PCI Express.
The widest range of image compression cores available anywhere, from JPEG through JPEG 2000.
Security-ready AES, MD5, and SHA encryption cores.
Peripherals such as controllers for smart card readers and video displays.
An assortment of synchronous UARTs and an SDLC for communications.
A variety of basic logic parts and models.
A cost-effective solution for extending product life through 2901 processors, Z80 support functions, controllers, peripherals, and many more replacement parts.
All CAST IP cores come complete and ready to use, and are backed with our widely-regarded expert support.
SoC Kernel IP Platforms
Get a head start on your 32-bit processor based systems with our SoC Kernels and pre-integrated IP (PiP) platforms.
SOC Kernels are:
pre-integrated,
processor agnostic, and
technology independent.
They combine essential software like device drivers and boot code with multiple IP cores — timers, memory controllers, etc. — in a verified package ready for system development.
SOC Kernels are reasy to expand into more complex systems, and several pre-expanded PIPs are available now.
Wednesday, September 17, 2008
On2 Technologies Announces New High Definition Hardware Encoder IP
The Hantro™ 7280 enables real-time video encoding up to 1280 x 1024 resolution for low-power chipsets
On2 Technologies (AMEX: ONT), the leader in video compression solutions, announced today the availability of the Hantro 7280 encoder Register Transfer Level (RTL) design. Supporting MPEG-4, H.263 and H.264 video, along with 16MP JPEG, the encoder is targeted for chipsets intended for devices with very low-power requirements such as: portable video cameras, mobile phones, remote security cameras, laptops and webcams. With a maximum resolution of 1280x1024 at 30 fps, the Hantro 7280 introduces a new level of performance and functionality.
Following the Hantro 6280, which was licensed by more than 15 leading chip manufacturers, the encoder brings further speed improvements to achieve resolutions up to 1280x1024 at 30 fps. Easily encoding full 720p H.264 at 30 fps in only 180 MHz clock frequency, the 7280 brings ultra-high performance to 65 nm and 90 nm low-power chipsets. Placing a CPU load of less than 1MHz, the Hantro 7280 allows even an entry level ARM9-based chipset to encode real-time HD H.264 video with plenty of headroom to spare. The new encoder also incorporates proprietary image stabilization technology which reduces the effects of camera shake prior to encoding resulting in higher quality video with better compression.
Optimized for rapid integration with ARM, MIPS and other embedded CPU and DSP cores, the Hantro 7280 marries high performance with ultra low-power and efficient silicon utilization. Silicon area can be further optimized for unique applications by selecting only the formats and screen resolutions required with area reduced to as small as 0.19 square millimeters per 139,000 gates. Additional area savings can be gained in a full codec solution by sharing internal memories with the Hantro 8190 multi-format decoder.
“For portable devices, battery-life is a critical success factor and manufacturers seek to optimize in every aspect.” says Eero Kaikkonen, Chief Marketing Officer at On2. “The 7280 requires only 12 mW to encode VGA H.264 in real-time. Although in practice it is not possible, theoretically an ARM 11 would require as much as 500mW to achieve the same performance.”
The Hantro 7280 is available now for licensing from On2. The product comes complete with RTL source code for VHDL or Verilog, an RTL test bench and test data, ANSI C driver source code and complete technical documentation.
On2 Technologies (AMEX: ONT), the leader in video compression solutions, announced today the availability of the Hantro 7280 encoder Register Transfer Level (RTL) design. Supporting MPEG-4, H.263 and H.264 video, along with 16MP JPEG, the encoder is targeted for chipsets intended for devices with very low-power requirements such as: portable video cameras, mobile phones, remote security cameras, laptops and webcams. With a maximum resolution of 1280x1024 at 30 fps, the Hantro 7280 introduces a new level of performance and functionality.
Following the Hantro 6280, which was licensed by more than 15 leading chip manufacturers, the encoder brings further speed improvements to achieve resolutions up to 1280x1024 at 30 fps. Easily encoding full 720p H.264 at 30 fps in only 180 MHz clock frequency, the 7280 brings ultra-high performance to 65 nm and 90 nm low-power chipsets. Placing a CPU load of less than 1MHz, the Hantro 7280 allows even an entry level ARM9-based chipset to encode real-time HD H.264 video with plenty of headroom to spare. The new encoder also incorporates proprietary image stabilization technology which reduces the effects of camera shake prior to encoding resulting in higher quality video with better compression.
Optimized for rapid integration with ARM, MIPS and other embedded CPU and DSP cores, the Hantro 7280 marries high performance with ultra low-power and efficient silicon utilization. Silicon area can be further optimized for unique applications by selecting only the formats and screen resolutions required with area reduced to as small as 0.19 square millimeters per 139,000 gates. Additional area savings can be gained in a full codec solution by sharing internal memories with the Hantro 8190 multi-format decoder.
“For portable devices, battery-life is a critical success factor and manufacturers seek to optimize in every aspect.” says Eero Kaikkonen, Chief Marketing Officer at On2. “The 7280 requires only 12 mW to encode VGA H.264 in real-time. Although in practice it is not possible, theoretically an ARM 11 would require as much as 500mW to achieve the same performance.”
The Hantro 7280 is available now for licensing from On2. The product comes complete with RTL source code for VHDL or Verilog, an RTL test bench and test data, ANSI C driver source code and complete technical documentation.
ChipX Adds More Than 60 Analog Functions to IP Portfolio
Easy to use, silicon proven, industrial-grade analog building blocks enable low-risk analog circuit integration in industrial, medical, military and aerospace mixed-signal ASICs
Santa Clara – September 15, 2008 – ChipX, Inc, a mixed-signal company providing the industry's broadest offering of low-risk ASIC solutions, today announced the addition of over 60 industrial-grade analog building blocks to its line-up of analog and mixed-signal IP. Following the company’s digital to analog converter family announcement in June 2008, ChipX is continuing on its quest to increase its analog and mixed-signal ASIC capabilities with a focus on Medical, Industrial, Military and Aerospace applications
Designed for signal conditioning, on-chip references, clocking, controlled reset, Input/Output and a variety of other analog functions, the analog building blocks are ideal for system-chip designs used in medical devices, industrial products, military and aerospace applications. Fully-characterized for Industrial temperature in high-volume CMOS process geometries of ChipX foundry partners, the analog building blocks can be combined with other proven ChipX IP or trusted 3rd party IP for System-on-Chip (SoC) designs.
“Our system architecture and analog team works with customers to come up with the best balance between on-chip and off-chip analog functions,” said Elie Massabki, Vice President of Marketing for ChipX. By using our proven catalog of analog building blocks and other IP, customers can integrate substantial parts of their system on one mixed-signal device to reduce system cost and lower implementation risk.”
Analog Building Block Catalog
The ChipX analog building block catalog consists of many general purpose functions, available in 250nm, 180nm and 130nm processes. Building blocks include analog switches and multiplexers, charge pumps, comparators, self-calibrated termination, reference resistors, reference voltage and reference current generators, oscillator circuits, power-on-reset generators, operational amplifiers and various I/Os including HSTL, SSTL 1.5/1.8/2.5/3.3, LVPECL and LVDS.
Each of the analog building block family members includes simulation models, extensive data sheets, and full design information. They can be integrated with the full range of ChipX building blocks – including 10-bit, 210Msps DAC, USB 2.0, PCI Express, DDR/DDR2, ARM(926) or BA12/22 processors to create a System on Chip (SoC) – in mixed-signal Hybrid ASIC, Embedded Array or Standard Cell products today.
About ChipX
ChipX, Inc. is a Mixed-Signal ASIC company with the broadest offering of value-added ASIC solutions, including Standard Cell, Structured ASIC and Hybrid ASIC technology. ChipX has unique expertise in PCI Express, USB 2.0, DDR/DDR2 and data conversion mixed-signal cores; all are silicon proven and certified and they can be integrated in customers’ ASICs with a record first-time to market success. ChipX products are widely used in industrial applications, medical equipment and military/aerospace systems. Headquartered in Santa Clara, CA, ChipX is a privately held corporation, with a Research and Development subsidiary in Israel. Investors include Elron Electronic Industries, Ltd. (NASDQ: ELRN),VantagePoint Venture Partners, Wasserstein Venture Capital, UMC and Needham Capital Partners.
Santa Clara – September 15, 2008 – ChipX, Inc, a mixed-signal company providing the industry's broadest offering of low-risk ASIC solutions, today announced the addition of over 60 industrial-grade analog building blocks to its line-up of analog and mixed-signal IP. Following the company’s digital to analog converter family announcement in June 2008, ChipX is continuing on its quest to increase its analog and mixed-signal ASIC capabilities with a focus on Medical, Industrial, Military and Aerospace applications
Designed for signal conditioning, on-chip references, clocking, controlled reset, Input/Output and a variety of other analog functions, the analog building blocks are ideal for system-chip designs used in medical devices, industrial products, military and aerospace applications. Fully-characterized for Industrial temperature in high-volume CMOS process geometries of ChipX foundry partners, the analog building blocks can be combined with other proven ChipX IP or trusted 3rd party IP for System-on-Chip (SoC) designs.
“Our system architecture and analog team works with customers to come up with the best balance between on-chip and off-chip analog functions,” said Elie Massabki, Vice President of Marketing for ChipX. By using our proven catalog of analog building blocks and other IP, customers can integrate substantial parts of their system on one mixed-signal device to reduce system cost and lower implementation risk.”
Analog Building Block Catalog
The ChipX analog building block catalog consists of many general purpose functions, available in 250nm, 180nm and 130nm processes. Building blocks include analog switches and multiplexers, charge pumps, comparators, self-calibrated termination, reference resistors, reference voltage and reference current generators, oscillator circuits, power-on-reset generators, operational amplifiers and various I/Os including HSTL, SSTL 1.5/1.8/2.5/3.3, LVPECL and LVDS.
Each of the analog building block family members includes simulation models, extensive data sheets, and full design information. They can be integrated with the full range of ChipX building blocks – including 10-bit, 210Msps DAC, USB 2.0, PCI Express, DDR/DDR2, ARM(926) or BA12/22 processors to create a System on Chip (SoC) – in mixed-signal Hybrid ASIC, Embedded Array or Standard Cell products today.
About ChipX
ChipX, Inc. is a Mixed-Signal ASIC company with the broadest offering of value-added ASIC solutions, including Standard Cell, Structured ASIC and Hybrid ASIC technology. ChipX has unique expertise in PCI Express, USB 2.0, DDR/DDR2 and data conversion mixed-signal cores; all are silicon proven and certified and they can be integrated in customers’ ASICs with a record first-time to market success. ChipX products are widely used in industrial applications, medical equipment and military/aerospace systems. Headquartered in Santa Clara, CA, ChipX is a privately held corporation, with a Research and Development subsidiary in Israel. Investors include Elron Electronic Industries, Ltd. (NASDQ: ELRN),VantagePoint Venture Partners, Wasserstein Venture Capital, UMC and Needham Capital Partners.
To develop or buy a Verification IP
Atul Bhatia, Director, nSys Design Systems
Independent Interpretation
The most important benefit of buying the VIP rather than making it is that a commercial VIP provides a totally independent, clear and unambiguous interpretation of the specifications of a protocol for which it is designed. Until the time when the specifications themselves are written such that they have no ambiguity, this independent interpretation is invaluable. It gets even more important when the specifications are those of a complex protocol. In case the commercial VIP is already proven by use with RTL designs of other users, the value increases to several times of its cost to the user. This is because the user is assured inter-operability and compliance due to the use of this VIP with other designs.
Availability of Test Suites
If the VIP is available not only with the Bus Function Models, Monitor and Protocol Checker but also with Test Suites, then the user is able to save considerable time that would have been spent in writing the test cases that are available as part of the Test Suites. Not only are the test cases difficult to identify and time-consuming, most engineers write them grudgingly. Availability of test cases in source code makes it easier to modify and create additional cases unique to the user’s designs.
Packaging
Just as a home-made dish cannot be packaged as attractively as the one that is available from a restaurant, an in-house VIP will also not be packaged as well as a commercial VIP. Some of the distinct features of the packaging that are very difficult to incorporate in an in-house VIP are: availability of a well-documented User Manual, Flash-based tutorials, comprehensive FAQs based upon queries faced by existing users, a self-service bug tracking portal, Application notes and a well designed GUI. In case the VIP provider is offering a family of VIPs, the additional features of packaging would be: consistency of interface, installation, operation, and documentation across the VIP family. Since the APIs for a family would be well thought out and consistent across the family of VIP, it would reduce the requirement of learning the API while using additional interfaces.
FPGA Designs
At the other end of the spectrum of the develop-or-buy decision are the FPGA developers who do not even consider using simulation for verification. They feel that they would find the bugs at the system level in any case and the bug would just require a change in the RTL rather than throw away the chip as would be the case for an ASIC developer. This belittles the complexity of FPGA designs brought about by increase in their size. Fortunately, FPGA developers are becoming aware of this and have begun verifying their designs extensively in simulation too. Especially since it is very easy to compute that the cost of a license of a commercial VIP may be less than the cost of one engineering man-month. We have not factored in the impact of the cost of delay in product which will be many times this cost.
RTL IP
One of the ways of overcoming the well known productivity gap is the use of Design or RTL IP. A 2002 study by Collett International Research revealed that 14 percent of all chips that failed had bugs in reused components or imported IP. The other key problem while using an IP is that its integration with rest of the design has to be thoroughly tested. Thus a VIP should be able to verify the IP at the block level and also provide features for System level verification to ensure the correctness of integration of the IP with rest of the design.
Bundled VIP
Some situations when the develop-or-buy decisions get difficult to make are when an RTL IP has been used for a while and can be expected to be bug-free or when an RTL IP is available with a VIP. It has been observed that even if an RTL IP is field-proven, it may still have several bugs that are brought out by a new design (as luck would have it). A free VIP that may be available with RTL IP unless it is from a 3rd party vendor is not good enough for use in a commercial project. In the case when a 3rd party VIP is available bundled with the IP, it is likely to have a reduced feature set sufficient to demonstrate the working of the IP and the VIP while the features required to perform verification of the IP as well as its integration with the rest of the design may not be available. In fact, the extra effort spent in using the free or scaled-down VIP is several times the cost of a good 3rd party full feature VIP.
Conclusion
Verification productivity that is required to meet the challenges of tomorrow can only be met by incorporating widely used and proven VIPs in the verification flow. A family of VIPs having consistency of interface as well as look and feel increases this productivity across projects. The case for developing a VIP can only be made for proprietary interfaces. For all other interfaces, it is better to buy rather than develop a VIP.
Independent Interpretation
The most important benefit of buying the VIP rather than making it is that a commercial VIP provides a totally independent, clear and unambiguous interpretation of the specifications of a protocol for which it is designed. Until the time when the specifications themselves are written such that they have no ambiguity, this independent interpretation is invaluable. It gets even more important when the specifications are those of a complex protocol. In case the commercial VIP is already proven by use with RTL designs of other users, the value increases to several times of its cost to the user. This is because the user is assured inter-operability and compliance due to the use of this VIP with other designs.
Availability of Test Suites
If the VIP is available not only with the Bus Function Models, Monitor and Protocol Checker but also with Test Suites, then the user is able to save considerable time that would have been spent in writing the test cases that are available as part of the Test Suites. Not only are the test cases difficult to identify and time-consuming, most engineers write them grudgingly. Availability of test cases in source code makes it easier to modify and create additional cases unique to the user’s designs.
Packaging
Just as a home-made dish cannot be packaged as attractively as the one that is available from a restaurant, an in-house VIP will also not be packaged as well as a commercial VIP. Some of the distinct features of the packaging that are very difficult to incorporate in an in-house VIP are: availability of a well-documented User Manual, Flash-based tutorials, comprehensive FAQs based upon queries faced by existing users, a self-service bug tracking portal, Application notes and a well designed GUI. In case the VIP provider is offering a family of VIPs, the additional features of packaging would be: consistency of interface, installation, operation, and documentation across the VIP family. Since the APIs for a family would be well thought out and consistent across the family of VIP, it would reduce the requirement of learning the API while using additional interfaces.
FPGA Designs
At the other end of the spectrum of the develop-or-buy decision are the FPGA developers who do not even consider using simulation for verification. They feel that they would find the bugs at the system level in any case and the bug would just require a change in the RTL rather than throw away the chip as would be the case for an ASIC developer. This belittles the complexity of FPGA designs brought about by increase in their size. Fortunately, FPGA developers are becoming aware of this and have begun verifying their designs extensively in simulation too. Especially since it is very easy to compute that the cost of a license of a commercial VIP may be less than the cost of one engineering man-month. We have not factored in the impact of the cost of delay in product which will be many times this cost.
RTL IP
One of the ways of overcoming the well known productivity gap is the use of Design or RTL IP. A 2002 study by Collett International Research revealed that 14 percent of all chips that failed had bugs in reused components or imported IP. The other key problem while using an IP is that its integration with rest of the design has to be thoroughly tested. Thus a VIP should be able to verify the IP at the block level and also provide features for System level verification to ensure the correctness of integration of the IP with rest of the design.
Bundled VIP
Some situations when the develop-or-buy decisions get difficult to make are when an RTL IP has been used for a while and can be expected to be bug-free or when an RTL IP is available with a VIP. It has been observed that even if an RTL IP is field-proven, it may still have several bugs that are brought out by a new design (as luck would have it). A free VIP that may be available with RTL IP unless it is from a 3rd party vendor is not good enough for use in a commercial project. In the case when a 3rd party VIP is available bundled with the IP, it is likely to have a reduced feature set sufficient to demonstrate the working of the IP and the VIP while the features required to perform verification of the IP as well as its integration with the rest of the design may not be available. In fact, the extra effort spent in using the free or scaled-down VIP is several times the cost of a good 3rd party full feature VIP.
Conclusion
Verification productivity that is required to meet the challenges of tomorrow can only be met by incorporating widely used and proven VIPs in the verification flow. A family of VIPs having consistency of interface as well as look and feel increases this productivity across projects. The case for developing a VIP can only be made for proprietary interfaces. For all other interfaces, it is better to buy rather than develop a VIP.
An Industry First: 8-Channel Analog Front End IC
IQ Analog now brings to market an industry first: an 8-channel, low power, high-performance Analog Front End Integrated Circuit (IC) for multi-channel applications such as MIMO radios.
After three years of development, IQ Analog announces the arrival of the IQA-F430 Octal Analog Front End (AFE), ushering in the next generation mixed signal front end platform for wireless and communication applications. According to Mike Kappes, President & CEO of IQ Analog, the IQA-F430 Octal AFE makes real the promise of integrating multiple discrete AFE devices into a single, cost effective and low power solution.
“IQ Analog is uniquely positioned to now offer multi-channel integration within low cost packaging constraints…we immediately address the wireless infrastructure market with a single IC that replaces the multi-chip solutions in use today…..” stated Kappes. As an example, Kappes points out that a typical MIMO configuration consists of 4 x 2 channel AFEs; this configuration is replaced with just a single, 8 channel IC chip from IQ Analog. In this system solution, not only is cost mitigated by the F430, but power consumption is radically minimized. IQ Analog’s F430 measures at 30mW per channel versus 300mW per channel for existing market offerings. Another hallmark of IQ Analog mixed signal technology; phenomenally small die size. The 8 way F430 is 16mm2, about 40% the size of comparable 2 channel AFEs.
The IQA F430 AFE is characterized by 8 independent 12-bit 80-Msps analog-to-digital converters (ADC’s) and 8 independent 12-bit 20-MHz bandwidth digital-to-analog converters (DAC’s) for the main signal paths and 8 auxiliary 12-bit 300-Ksps ADC’s and 8 auxiliary 12-bit 300-Ksps DAC’s for ancillary functions. The F430 is currently fabricated in a 130nm CMOS process; Kappes and his team plan to move to 65nm before the end of 2008.
About IQ Analog
IQ Analog is a privately held fabless semiconductor company headquartered in San Diego, CA. The company was founded by industry veterans who previously led engineering efforts at leading System-on-Chip (SoC) companies including Broadcom, Conexant, Innovent, and Brooktree. In addition to its newly released IC product family, the company offers analog interface components including a range of ADCs and AFEs in 180nm /130nm/90nm/65nm. IQ Analog provides world class design and customization services to support its IP portfolio. For more information, visit www.iqanalog.com or contact info@iqanalog.com.
After three years of development, IQ Analog announces the arrival of the IQA-F430 Octal Analog Front End (AFE), ushering in the next generation mixed signal front end platform for wireless and communication applications. According to Mike Kappes, President & CEO of IQ Analog, the IQA-F430 Octal AFE makes real the promise of integrating multiple discrete AFE devices into a single, cost effective and low power solution.
“IQ Analog is uniquely positioned to now offer multi-channel integration within low cost packaging constraints…we immediately address the wireless infrastructure market with a single IC that replaces the multi-chip solutions in use today…..” stated Kappes. As an example, Kappes points out that a typical MIMO configuration consists of 4 x 2 channel AFEs; this configuration is replaced with just a single, 8 channel IC chip from IQ Analog. In this system solution, not only is cost mitigated by the F430, but power consumption is radically minimized. IQ Analog’s F430 measures at 30mW per channel versus 300mW per channel for existing market offerings. Another hallmark of IQ Analog mixed signal technology; phenomenally small die size. The 8 way F430 is 16mm2, about 40% the size of comparable 2 channel AFEs.
The IQA F430 AFE is characterized by 8 independent 12-bit 80-Msps analog-to-digital converters (ADC’s) and 8 independent 12-bit 20-MHz bandwidth digital-to-analog converters (DAC’s) for the main signal paths and 8 auxiliary 12-bit 300-Ksps ADC’s and 8 auxiliary 12-bit 300-Ksps DAC’s for ancillary functions. The F430 is currently fabricated in a 130nm CMOS process; Kappes and his team plan to move to 65nm before the end of 2008.
About IQ Analog
IQ Analog is a privately held fabless semiconductor company headquartered in San Diego, CA. The company was founded by industry veterans who previously led engineering efforts at leading System-on-Chip (SoC) companies including Broadcom, Conexant, Innovent, and Brooktree. In addition to its newly released IC product family, the company offers analog interface components including a range of ADCs and AFEs in 180nm /130nm/90nm/65nm. IQ Analog provides world class design and customization services to support its IP portfolio. For more information, visit www.iqanalog.com or contact info@iqanalog.com.
Tuesday, July 29, 2008
IP Cores for Education
In electronic design and electronic design automation, an intellectual property (IP) block—or IP core—is a unit of reusable design, the use of which has been licensed to a third party. The term is derived from the licensing of the intellectual property rights, such as patents and copyrights, that subsist in the design.
IP cores are for hardware design what libraries are for computer programming. They are typically used much in the style and manner of a discrete integrated circuit on a PCB, where the "circuit board" is a larger ASIC or FPGA design. An IP core commonly takes the form of a computer program written in some HDL—such as Verilog, VHDL, or SystemC—but it can also be a netlist or physical layout, especially in analog electronics.
Altera provides a library of SOPC Builder components (IP cores), which are listed in the table below, for all I/O devices on the DE1 and DE2 boards. You can use these components as part of the SOPC Builder tool in the Quartus® II software. They allow you to easily create Nios® II systems that can access the I/O devices on the DE1 and DE2 boards. Also provided are the associated software drivers that you can incorporate into an Altera® Debug Client project (or an Altera Nios II IDE project). You can install the components in the library using the installer found in the table or download individual IP cores independently. If the IP cores are downloaded independently, you must place them in your project directory or in the sopc_builder\components within the Quartus II install path.
Note: The University Program IP cores are still under development. Several of the cores are available in beta release version. The beta release is supported directly by the Altera Debug Client.
Table 1. University Program IP Cores
IP Cores Description PDF ZIP Development Board Supported
Embedded Processors
Nios II Altera's embedded soft processor
Nios II DE1, DE2
IP Core Bundle
Installer Installs all the available IP cores. The IP cores are listed below. EXE DE1, DE2
Release Notes Description of releases to date TXT
Memory Controller
SRAM Provides read/write access to the SRAM chip PDF ZIP DE1, DE2
SDRAM Provides read/write access to the SDRAM chip and also refreshes the chip automatically PDF ZIP DE1, DE2
FLASH Not available PDF ZIP DE1, DE2
SD Card Not available PDF ZIP DE1, DE2
Communication
RS232 UART Provides a UART over the RS232 port PDF ZIP DE1, DE2
JTAG UART Provides a UART over the JTAG PDF DE1, DE2
Ethernet Not available PDF ZIP DE2
IrDA Provides a UART over the IrDA port PDF ZIP DE2
USB Not available PDF ZIP DE2
Audio/Video
Audio/Video Configuration Automatically configures the audio and video chip PDF ZIP DE1, DE2
Audio In/Out Provides two FIFOs for audio data PDF ZIP DE1, DE2
Video Out Creates timing information for VGA display and has frame buffers for storing picture information PDF ZIP DE1, DE2
Video In Not available PDF ZIP DE2
Input/Output
Parallel Port A generic parallel input/output interface PDF ZIP DE1, DE2
PS/2 Port Serial connection for the PS/2 port PDF ZIP DE1, DE2
16x2 LCD Character Display Connection to the LCD character display PDF ZIP DE2
Avalon® to External Bus Bridge A bus-like interface for a slave device PDF ZIP DE1, DE2
External Bus to Avalon Bridge A bus-like interface for a master device PDF ZIP DE1, DE2
The above IP cores have been developed to support Altera's University Program and its DE1 and DE2 development and education boards. It is important to note that Altera provides a wide range of IP cores to implement industry-standard designs (such as a USB controller or echo cancellation circuitry) and speed system engineering. Altera IP cores are designed to take advantage of the unique features of FPGAs.
Altera offers IP megafunctions for the following technology types:
Embedded Processors (Nios II processors, microcontrollers)
Interfaces and Peripherals (DDR2, PCI, PCI Express)
Digital Signal Processing (fast Fourier transform)
Communications (various physical layers)
View the full listing of available IP cores at the Altera IP MegaStore™.
Commercial IP Core Requests
The Altera University Program provides Altera-developed IP at no charge to qualified research projects at universities. Please contact university@altera.com for more information.
IP cores are for hardware design what libraries are for computer programming. They are typically used much in the style and manner of a discrete integrated circuit on a PCB, where the "circuit board" is a larger ASIC or FPGA design. An IP core commonly takes the form of a computer program written in some HDL—such as Verilog, VHDL, or SystemC—but it can also be a netlist or physical layout, especially in analog electronics.
Altera provides a library of SOPC Builder components (IP cores), which are listed in the table below, for all I/O devices on the DE1 and DE2 boards. You can use these components as part of the SOPC Builder tool in the Quartus® II software. They allow you to easily create Nios® II systems that can access the I/O devices on the DE1 and DE2 boards. Also provided are the associated software drivers that you can incorporate into an Altera® Debug Client project (or an Altera Nios II IDE project). You can install the components in the library using the installer found in the table or download individual IP cores independently. If the IP cores are downloaded independently, you must place them in your project directory or in the sopc_builder\components within the Quartus II install path.
Note: The University Program IP cores are still under development. Several of the cores are available in beta release version. The beta release is supported directly by the Altera Debug Client.
Table 1. University Program IP Cores
IP Cores Description PDF ZIP Development Board Supported
Embedded Processors
Nios II Altera's embedded soft processor
Nios II DE1, DE2
IP Core Bundle
Installer Installs all the available IP cores. The IP cores are listed below. EXE DE1, DE2
Release Notes Description of releases to date TXT
Memory Controller
SRAM Provides read/write access to the SRAM chip PDF ZIP DE1, DE2
SDRAM Provides read/write access to the SDRAM chip and also refreshes the chip automatically PDF ZIP DE1, DE2
FLASH Not available PDF ZIP DE1, DE2
SD Card Not available PDF ZIP DE1, DE2
Communication
RS232 UART Provides a UART over the RS232 port PDF ZIP DE1, DE2
JTAG UART Provides a UART over the JTAG PDF DE1, DE2
Ethernet Not available PDF ZIP DE2
IrDA Provides a UART over the IrDA port PDF ZIP DE2
USB Not available PDF ZIP DE2
Audio/Video
Audio/Video Configuration Automatically configures the audio and video chip PDF ZIP DE1, DE2
Audio In/Out Provides two FIFOs for audio data PDF ZIP DE1, DE2
Video Out Creates timing information for VGA display and has frame buffers for storing picture information PDF ZIP DE1, DE2
Video In Not available PDF ZIP DE2
Input/Output
Parallel Port A generic parallel input/output interface PDF ZIP DE1, DE2
PS/2 Port Serial connection for the PS/2 port PDF ZIP DE1, DE2
16x2 LCD Character Display Connection to the LCD character display PDF ZIP DE2
Avalon® to External Bus Bridge A bus-like interface for a slave device PDF ZIP DE1, DE2
External Bus to Avalon Bridge A bus-like interface for a master device PDF ZIP DE1, DE2
The above IP cores have been developed to support Altera's University Program and its DE1 and DE2 development and education boards. It is important to note that Altera provides a wide range of IP cores to implement industry-standard designs (such as a USB controller or echo cancellation circuitry) and speed system engineering. Altera IP cores are designed to take advantage of the unique features of FPGAs.
Altera offers IP megafunctions for the following technology types:
Embedded Processors (Nios II processors, microcontrollers)
Interfaces and Peripherals (DDR2, PCI, PCI Express)
Digital Signal Processing (fast Fourier transform)
Communications (various physical layers)
View the full listing of available IP cores at the Altera IP MegaStore™.
Commercial IP Core Requests
The Altera University Program provides Altera-developed IP at no charge to qualified research projects at universities. Please contact university@altera.com for more information.
Monday, July 21, 2008
Recore Systems New IP
Recore Systems licenses innovative IP for creating advanced digital signal processing platform chips. Recore’s Montium® technology comprises processor cores, design tools for easy integration in customer solutions and ready-to-use applications. Recore offers application implementations for Montium based platforms, IDE tools and hardware IPs.
Recore’s technology enables ultra energy-efficient digital signal processing in products such as cell phones, digital radios/TVs and infotainment and navigation systems. Reuse of Recore’s IP alleviates the avalanching design complexity and costs of today’s chip development. Montium technology allows time multiplexing of different functions on the same hardware and offers a unique combination of flexibility, high performance, low power and low costs.
An excellent engineering team is devoted to create supreme systems-on-chip, with exceptional power and performance characteristics. Recore attracts the best people into all levels of the organization and encourages a stimulating environment, with strong links to leading research centers.
3 Product(s) Listed
Part Number Product Description
Montium DAB/DAB+ Viterbi Decoder Soft IP core implementation of the Viterbi algorithm for Montium tile processors optimized for DAB/DAB+ applications
Montium® FFT/IFFT IP Core FFT/IFFT implementation for Montium Tile Processors
Montium Tile Processor (TP) Dynamically Reconfigurable Digital Signal Processing Tile Processor
Recore’s technology enables ultra energy-efficient digital signal processing in products such as cell phones, digital radios/TVs and infotainment and navigation systems. Reuse of Recore’s IP alleviates the avalanching design complexity and costs of today’s chip development. Montium technology allows time multiplexing of different functions on the same hardware and offers a unique combination of flexibility, high performance, low power and low costs.
An excellent engineering team is devoted to create supreme systems-on-chip, with exceptional power and performance characteristics. Recore attracts the best people into all levels of the organization and encourages a stimulating environment, with strong links to leading research centers.
3 Product(s) Listed
Part Number Product Description
Montium DAB/DAB+ Viterbi Decoder Soft IP core implementation of the Viterbi algorithm for Montium tile processors optimized for DAB/DAB+ applications
Montium® FFT/IFFT IP Core FFT/IFFT implementation for Montium Tile Processors
Montium Tile Processor (TP) Dynamically Reconfigurable Digital Signal Processing Tile Processor
HDL Design House New IP
HDL Design House is a fast growing privately owned company focused on providing synthesizable VHDL/Verilog IP cores, ASIC (SoC) or FPGA design and design verification services.
HDL Design House was incorporated in March of 1999 with the mission to offer world class hardware design services to international customers. The founders have more then 10 years as consulting experts in ASIC/FPGA design for local and international customers. The strong experience and professional background acquired during this period, supplemented by customer satisfaction, encouraged them to found their own company and start to offer hardware design services.
The company has strong background in telecommunications, DSP, computer architecture, high performance computer arithmetic, and different communication protocols. Actively cooperating with USA companies on leading high-tech projects, HDL Design House engineering staff acquired and developed world class expertise in complex ASIC/FPGA design and design management, design verification, and related skills.
HDL Design House has internal IP core development program. Still it can develop IP cores according to the customer specification.
We favor long-term relationship with our customers.
11 Product(s) Listed
Part Number Product Description
HIP 3200 UniPro Soft IP Core
HIP 2900 BCH Codec
HIP 4000 Golay Encoder/Decoder IP Core
HIP 2400 Reed Solomon Encoder IP Core
HIP 2500 Reed Solomon Decoder IP Core
HIP 3000 APB SPI Lite IP Core
HMC FIDWT 39510 Forward and Inverse Discrete Wavelet Transform
HMC FFT 31510 1024-Point Complex FFT/IFFT
HIP 1100 DES/TDES - Full hardware implementation of NIST FIPS PUB 46-3 algorithm (DES/TDES). OCP/AMBA bus interfaces
HIP 1000 AES - Full hardware implementation of NIST FIPS PUB 197 algorithm. 128 bit data and programable 128/192/256 key length
IEEE 1284 IEEE 1284 Parallel Port Controller
HDL Design House was incorporated in March of 1999 with the mission to offer world class hardware design services to international customers. The founders have more then 10 years as consulting experts in ASIC/FPGA design for local and international customers. The strong experience and professional background acquired during this period, supplemented by customer satisfaction, encouraged them to found their own company and start to offer hardware design services.
The company has strong background in telecommunications, DSP, computer architecture, high performance computer arithmetic, and different communication protocols. Actively cooperating with USA companies on leading high-tech projects, HDL Design House engineering staff acquired and developed world class expertise in complex ASIC/FPGA design and design management, design verification, and related skills.
HDL Design House has internal IP core development program. Still it can develop IP cores according to the customer specification.
We favor long-term relationship with our customers.
11 Product(s) Listed
Part Number Product Description
HIP 3200 UniPro Soft IP Core
HIP 2900 BCH Codec
HIP 4000 Golay Encoder/Decoder IP Core
HIP 2400 Reed Solomon Encoder IP Core
HIP 2500 Reed Solomon Decoder IP Core
HIP 3000 APB SPI Lite IP Core
HMC FIDWT 39510 Forward and Inverse Discrete Wavelet Transform
HMC FFT 31510 1024-Point Complex FFT/IFFT
HIP 1100 DES/TDES - Full hardware implementation of NIST FIPS PUB 46-3 algorithm (DES/TDES). OCP/AMBA bus interfaces
HIP 1000 AES - Full hardware implementation of NIST FIPS PUB 197 algorithm. 128 bit data and programable 128/192/256 key length
IEEE 1284 IEEE 1284 Parallel Port Controller
Denali Announces New LPDDR2 Memory Controller and PHY Solution
First Provider of Memory Controller and PHY Solution to Support LPDDR2 in Next-Generation Mobile and Embedded Applications
SUNNYVALE, Calif. -- July 21, 2008 -- Denali, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its Databahn(TM) memory controller and PHY IP supports the pre-released LPDDR2 specification, as currently defined by JEDEC -- the leading developer of standards for the solid-state industry. Chip designers and system architects desiring to upgrade to LPDDR2 can learn more about Denali's new upcoming LPDDR2 offering, which will include both varieties of SDRAM (S2/S4) in the memory controller and PHY IP and support for Non-Volatile Memory (NVM) by attending the MemCon presentation, "Next-Generation Low-Power LPDDR2 Memories: How to Use Them in Your Mobile and Embedded Designs" at 1:30pm on Wednesday, July 23 in Santa Clara, CA. Denali's Databahn LPDDR2 memory controller and PHY will be well suited for low power and embedded system designs which target applications as cell phones, ultra-mobile PCs, and consumer applications, addressing design requirements of density, speed, and power.
"We are pleased to see member companies introduce next-generation technologies that fully support the LPDDR2 industry specification. It is this type of advanced industry adoption that helps to establish high quality and reliability benchmarks required for low power and embedded system memory design," said Roger Isaac, chair for the JEDEC JC-42.6 Low Power Memory Committee. "Denali is an active committee participant, working closely with memory vendors like Spansion to provide valuable recommendations toward the development of the specification."
Denali's LPDDR2 memory controller and PHY will support the full specification when released by JEDEC. LPDDR2 addresses the needs of mobile and consumer systems where the "PC memory" devices, DDR2 and DDR3, are unsuitable, as LPDDR2 offers a low power, low voltage, low pin-count memory in a range of densities and speeds that are closely matched to the needs of those mobile and consumer systems. In addition, LPDDR2 was designed to allow sharing of SDRAM and NVM memory on the same bus, which is extremely difficult in PC memory technologies. For immediate availability of a C-model, in advance of the silicon IP for Denali's Databahn LPDDR2 memory controller and PHY, contact sales@denali.com.
"Many of our customers are looking for ways to upgrade to new controller technologies and are faced with several challenges," states Marc Greenberg, director of Technical Marketing for Databahn products at Denali Software. "Many of the LPDDR2 features are derived from the best features of the LPDDR1, DDR2 and DDR3 technologies that we already support. This gives Denali an accelerated position to support the LPDDR2 architecture and continue to provide our customers with high-quality, interoperable, and configurable IP solutions."
About Databahn Solutions
Denali's Databahn DDR DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, and LP-DDR devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification test bench, static timing analysis (STA) scripts, programmable register settings, documentation, I/O pads and packaging. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://www.denali.com/dram.
About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.
SUNNYVALE, Calif. -- July 21, 2008 -- Denali, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its Databahn(TM) memory controller and PHY IP supports the pre-released LPDDR2 specification, as currently defined by JEDEC -- the leading developer of standards for the solid-state industry. Chip designers and system architects desiring to upgrade to LPDDR2 can learn more about Denali's new upcoming LPDDR2 offering, which will include both varieties of SDRAM (S2/S4) in the memory controller and PHY IP and support for Non-Volatile Memory (NVM) by attending the MemCon presentation, "Next-Generation Low-Power LPDDR2 Memories: How to Use Them in Your Mobile and Embedded Designs" at 1:30pm on Wednesday, July 23 in Santa Clara, CA. Denali's Databahn LPDDR2 memory controller and PHY will be well suited for low power and embedded system designs which target applications as cell phones, ultra-mobile PCs, and consumer applications, addressing design requirements of density, speed, and power.
"We are pleased to see member companies introduce next-generation technologies that fully support the LPDDR2 industry specification. It is this type of advanced industry adoption that helps to establish high quality and reliability benchmarks required for low power and embedded system memory design," said Roger Isaac, chair for the JEDEC JC-42.6 Low Power Memory Committee. "Denali is an active committee participant, working closely with memory vendors like Spansion to provide valuable recommendations toward the development of the specification."
Denali's LPDDR2 memory controller and PHY will support the full specification when released by JEDEC. LPDDR2 addresses the needs of mobile and consumer systems where the "PC memory" devices, DDR2 and DDR3, are unsuitable, as LPDDR2 offers a low power, low voltage, low pin-count memory in a range of densities and speeds that are closely matched to the needs of those mobile and consumer systems. In addition, LPDDR2 was designed to allow sharing of SDRAM and NVM memory on the same bus, which is extremely difficult in PC memory technologies. For immediate availability of a C-model, in advance of the silicon IP for Denali's Databahn LPDDR2 memory controller and PHY, contact sales@denali.com.
"Many of our customers are looking for ways to upgrade to new controller technologies and are faced with several challenges," states Marc Greenberg, director of Technical Marketing for Databahn products at Denali Software. "Many of the LPDDR2 features are derived from the best features of the LPDDR1, DDR2 and DDR3 technologies that we already support. This gives Denali an accelerated position to support the LPDDR2 architecture and continue to provide our customers with high-quality, interoperable, and configurable IP solutions."
About Databahn Solutions
Denali's Databahn DDR DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, and LP-DDR devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification test bench, static timing analysis (STA) scripts, programmable register settings, documentation, I/O pads and packaging. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://www.denali.com/dram.
About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.
Thursday, July 17, 2008
Gaisler Research AB Silicon IP Cores
Gaisler Research AB is a provider of SoC solutions for exceptionally competitive markets such as Aerospace, Military and demanding Commercial applications. The Gaisler Research's products consist of user-customizable 32-bit SPARC V8 processor cores, peripheral IP-cores and associated software and development tools. Gaisler Research solutions help companies develop highly competitive customer and application-specific SoC designs.
20 Product(s) Listed
Part Number Product Description
GRLIB Configurable AMBA bus SoC platform
LOGAN On-Chip Logic Analyzer
GRUSBHC USB 2.0 Host Controller
AHB2AHB Uni-directional AMBA AHB to AHB bridge
AHBBRIDGE Bi-directional AMBA AHB/AHB bridge
GRCAN CAN 2.0 Controller with DMA
RS_GF4 Reed-Solomon Memory Protection Codec
SSRCRTL 32-bit SSRAM/PROM Controller
SRCTRL 32-bit SRAM/PROM Controller
SDCRTL 32/64-bit PC133 SDRAM Controller
DDRSPA Single-port 16/32/64-bit DDR266 Controller
GRPCI 32-bit PCI Bus Master/Target
LEON3 32-bit SPARC V8 processor
GRETH_GBIT 10/100/1000 MBit Ethernet MAC
GRECC Elliptic Curve Cryptography (ECC) core with AMBA APB interface
GRAES Advanced Encryption Standard (AES-128) core with AMBA AHB interface
GRETH 10/100 Mbit Ethernet MAC
GRSPW Spacewire Codec with AHB host interface
GR1553 AMBA interface for Actel MIL-STD-1553B Cores
GRFPU-1 Single- and double-precision IEEE-754 floating-point unit
20 Product(s) Listed
Part Number Product Description
GRLIB Configurable AMBA bus SoC platform
LOGAN On-Chip Logic Analyzer
GRUSBHC USB 2.0 Host Controller
AHB2AHB Uni-directional AMBA AHB to AHB bridge
AHBBRIDGE Bi-directional AMBA AHB/AHB bridge
GRCAN CAN 2.0 Controller with DMA
RS_GF4 Reed-Solomon Memory Protection Codec
SSRCRTL 32-bit SSRAM/PROM Controller
SRCTRL 32-bit SRAM/PROM Controller
SDCRTL 32/64-bit PC133 SDRAM Controller
DDRSPA Single-port 16/32/64-bit DDR266 Controller
GRPCI 32-bit PCI Bus Master/Target
LEON3 32-bit SPARC V8 processor
GRETH_GBIT 10/100/1000 MBit Ethernet MAC
GRECC Elliptic Curve Cryptography (ECC) core with AMBA APB interface
GRAES Advanced Encryption Standard (AES-128) core with AMBA AHB interface
GRETH 10/100 Mbit Ethernet MAC
GRSPW Spacewire Codec with AHB host interface
GR1553 AMBA interface for Actel MIL-STD-1553B Cores
GRFPU-1 Single- and double-precision IEEE-754 floating-point unit
Aeroflex Incorporated Announces the Purchase of Gaisler Research AB
Aeroflex Incorporated today announced the acquisition of Gaisler Research AB, a privately held company, located in Gothenburg, Sweden.
Gaisler is a world leader in the development and support of IP cores and development tools for commercial and aerospace embedded processors based on the SPARC architecture. Gaisler’s flagship product is the LEON synthesizable processor which includes a full development environment and a library of IP support cores (GRLIB). The LEON processor architecture is an established solution for commercial and aerospace markets providing the designer with a flexible design environment for customization to individual requirements. Established in 2001, the Gaisler core design team is positioned as the pre-eminent processor design team for European markets with complete in-house design facilities for microprocessor, ASIC and field programmable gate array-based designs. With over 40 years of combined staff design experience, Gaisler has been involved in establishing past and current European standards for processor and ASIC development.
John Buyko, President, Aeroflex Microelectronic Solutions said, “Aeroflex is pleased that Gaisler Research is joining our team. This strategic acquisition provides Aeroflex with immediate improvement and synergy in our IP, software, and microprocessor design expertise, product solutions and technology roadmaps. The Gaisler portfolio will provide significant complimentary enhancements to our existing portfolio and further solidifies Aeroflex’s position as a leading supplier to our customers.”
About Aeroflex
Aeroflex Incorporated is a global provider of high technology solutions to the aerospace, defense and broadband communications markets. The Company’s diverse technologies allow it to design, develop, manufacture and market a broad range of test, measurement and microelectronic products. Additional information concerning Aeroflex Incorporated can be found on the Company’s website: www.aeroflex.com.
Gaisler is a world leader in the development and support of IP cores and development tools for commercial and aerospace embedded processors based on the SPARC architecture. Gaisler’s flagship product is the LEON synthesizable processor which includes a full development environment and a library of IP support cores (GRLIB). The LEON processor architecture is an established solution for commercial and aerospace markets providing the designer with a flexible design environment for customization to individual requirements. Established in 2001, the Gaisler core design team is positioned as the pre-eminent processor design team for European markets with complete in-house design facilities for microprocessor, ASIC and field programmable gate array-based designs. With over 40 years of combined staff design experience, Gaisler has been involved in establishing past and current European standards for processor and ASIC development.
John Buyko, President, Aeroflex Microelectronic Solutions said, “Aeroflex is pleased that Gaisler Research is joining our team. This strategic acquisition provides Aeroflex with immediate improvement and synergy in our IP, software, and microprocessor design expertise, product solutions and technology roadmaps. The Gaisler portfolio will provide significant complimentary enhancements to our existing portfolio and further solidifies Aeroflex’s position as a leading supplier to our customers.”
About Aeroflex
Aeroflex Incorporated is a global provider of high technology solutions to the aerospace, defense and broadband communications markets. The Company’s diverse technologies allow it to design, develop, manufacture and market a broad range of test, measurement and microelectronic products. Additional information concerning Aeroflex Incorporated can be found on the Company’s website: www.aeroflex.com.
Tensilica Appoints Semiconductor Industry Veteran Jack Guedj as New President and CEO
Founder Chris Rowen Becomes CTO to Drive Advanced Processor Technology
SANTA CLARA, Calif. – July 16, 2008 - Expanding its executive team with the talented leadership required to take the company into its next phase of growth, Tensilica, Inc. today announced it has appointed Dr. Jack Guedj, Ph.D. as the company’s president and chief executive officer (CEO). Guedj has extensive experience as a senior executive with a variety of fast-growing start-ups and high-profile semiconductor companies focused in high-performance communications and multimedia. He succeeds Dr. Chris Rowen, founder of Tensilica, who is now the company’s chief technology officer (CTO), driving advanced processor technology and applications in close partnership with Tensilica’s strategic customers. Rowen will continue to serve on the Tensilica board of directors.
“Tensilica’s customizable and standard processors are used broadly by a growing portfolio of customers who realize the benefits of flexible, optimized processor cores,” said Chris Rowen. “As our products continue to be adopted by an increasing customer base, the company is experiencing significant financial and operational growth, requiring the strengthening of our leadership team. Jack’s proven track record as a successful, savvy business leader makes him the ideal candidate to lead Tensilica at this exciting time.”
Rowen’s transition to the CTO position will enable him to fully focus on driving the long-term evolution of the customizable processor technology and its use by strategic customers. As founder of Tensilica in 1997 and inventor of its groundbreaking Xtensa processor technology and design methodology, he will continue to be an integral part of the company’s growth strategy. Under his guidance, Tensilica has secured over 130 licensees with a run rate of over 200 million processor cores shipped per year.
“I believe there is opportunity for substantial growth in Tensilica’s customizable processors and complete standard IP cores, in particular, in the consumer multimedia, wireless and wired communications, and computing application segments,” said Guedj. “Tensilica’s patented, automated processor design tools help designers quickly craft the best price/performance processors, lowering risk and providing the ability to evolve the hardware via programmability..”
Most recently, Guedj was president and CEO of Magnum Semiconductor, a leading provider of chips, software, and platforms for consumer entertainment and professional broadcast. Guedj spun Magnum out of Cirrus Logic in 2005. Under his leadership, he successfully led Magnum’s growth from its founding stage through the acquisition of LSI Logic’s consumer product group. Prior to Cirrus Logic, he was president of TVIA, a leading provider of digital display processors, and he led the company’s initial public offering in 2000. He is also a former vice president of sales and marketing at video set-top box and chip supplier, Faroudja, and director of digital media/residential broadband segments at National Semiconductor. He holds master’s and doctorate degrees in electronics from the University of Paris, as well as a master’s degree in business from UCLA.
“Jack’s proven track record gives him the experience Tensilica needs as it comes of age as a major supplier of optimized processor cores,” stated Harvey Jones, Tensilica’s chairman of the board. “The combination of these two highly talented top executives really strengthens the management team for the growth the company is already experiencing.”
About Tensilica
Tensilica, Inc., is the recognized leader in customizable and standard processors and DSPs for flexible audio, video, imaging, security, networking, and baseband signal processing. The modern design behind all of Tensilica’s processor cores powers top tier semiconductor companies, innovative start-ups, and system OEMs for high-volume products including mobile phones and other wireless devices, computer peripherals, storage devices, networking and communications equipment, and consumer electronics devices including portable media players, digital TV, and broadband set top boxes. For more information on Tensilica’s patented, benchmark-proven processors, visit www.tensilica.com.
SANTA CLARA, Calif. – July 16, 2008 - Expanding its executive team with the talented leadership required to take the company into its next phase of growth, Tensilica, Inc. today announced it has appointed Dr. Jack Guedj, Ph.D. as the company’s president and chief executive officer (CEO). Guedj has extensive experience as a senior executive with a variety of fast-growing start-ups and high-profile semiconductor companies focused in high-performance communications and multimedia. He succeeds Dr. Chris Rowen, founder of Tensilica, who is now the company’s chief technology officer (CTO), driving advanced processor technology and applications in close partnership with Tensilica’s strategic customers. Rowen will continue to serve on the Tensilica board of directors.
“Tensilica’s customizable and standard processors are used broadly by a growing portfolio of customers who realize the benefits of flexible, optimized processor cores,” said Chris Rowen. “As our products continue to be adopted by an increasing customer base, the company is experiencing significant financial and operational growth, requiring the strengthening of our leadership team. Jack’s proven track record as a successful, savvy business leader makes him the ideal candidate to lead Tensilica at this exciting time.”
Rowen’s transition to the CTO position will enable him to fully focus on driving the long-term evolution of the customizable processor technology and its use by strategic customers. As founder of Tensilica in 1997 and inventor of its groundbreaking Xtensa processor technology and design methodology, he will continue to be an integral part of the company’s growth strategy. Under his guidance, Tensilica has secured over 130 licensees with a run rate of over 200 million processor cores shipped per year.
“I believe there is opportunity for substantial growth in Tensilica’s customizable processors and complete standard IP cores, in particular, in the consumer multimedia, wireless and wired communications, and computing application segments,” said Guedj. “Tensilica’s patented, automated processor design tools help designers quickly craft the best price/performance processors, lowering risk and providing the ability to evolve the hardware via programmability..”
Most recently, Guedj was president and CEO of Magnum Semiconductor, a leading provider of chips, software, and platforms for consumer entertainment and professional broadcast. Guedj spun Magnum out of Cirrus Logic in 2005. Under his leadership, he successfully led Magnum’s growth from its founding stage through the acquisition of LSI Logic’s consumer product group. Prior to Cirrus Logic, he was president of TVIA, a leading provider of digital display processors, and he led the company’s initial public offering in 2000. He is also a former vice president of sales and marketing at video set-top box and chip supplier, Faroudja, and director of digital media/residential broadband segments at National Semiconductor. He holds master’s and doctorate degrees in electronics from the University of Paris, as well as a master’s degree in business from UCLA.
“Jack’s proven track record gives him the experience Tensilica needs as it comes of age as a major supplier of optimized processor cores,” stated Harvey Jones, Tensilica’s chairman of the board. “The combination of these two highly talented top executives really strengthens the management team for the growth the company is already experiencing.”
About Tensilica
Tensilica, Inc., is the recognized leader in customizable and standard processors and DSPs for flexible audio, video, imaging, security, networking, and baseband signal processing. The modern design behind all of Tensilica’s processor cores powers top tier semiconductor companies, innovative start-ups, and system OEMs for high-volume products including mobile phones and other wireless devices, computer peripherals, storage devices, networking and communications equipment, and consumer electronics devices including portable media players, digital TV, and broadband set top boxes. For more information on Tensilica’s patented, benchmark-proven processors, visit www.tensilica.com.
Tuesday, July 15, 2008
Intel And Micron First To Deliver Sub-40 Nanometer NAND Flash Memory Device
New 34 Nanometer 32 Gigabit NAND Chip is Industry’s Most Advanced NAND Process Technology Available Enabling Increased Storage Capacity in Small Form-Factor Applications
Boise, Idaho and Santa Clara, Calif. , Thursday, May 29, 2008 – Today Intel Corporation and Micron Technology, Inc. introduced the industry’s first sub-40 nanometer (nm) NAND memory device, unveiling a 34nm 32 gigabit (Gb) multi-level cell chip. This process technology was jointly developed by Intel and Micron and manufactured by the companies’ NAND flash joint venture, IM Flash Technologies (IMFT). It is the smallest NAND process geometry on the market. The 32 Gb NAND chip is the only monolithic device at this density that fits into a standard 48-lead thin small-outline package (TSOP), providing a cost-effective path to higher densities in existing applications. Shipments of customer samples begin in June and mass production is expected during the second half of this calendar year.
“This new 32 Gb device provides the best bit storage density available in the industry,” said Brian Shirley, vice president of Micron’s Memory Group. “Together with our partners at Intel, we’re proud to have now taken the lead in production process technology.”
“The introduction of 34nm process technology highlights IMFT’s rapid progress and moves us to the forefront of NAND process technology,” said Pete Hazen, director of marketing, Intel NAND Products Group. “These advancements will expand the value proposition and accelerate the adoption of solid-state drive (SSD) solutions in computing platforms.”
The 34nm 32 Gb chips will be manufactured on 300 millimeter wafers, each producing approximately 1.6 terabytes of NAND. Measuring just 172mm², less than the size of a thumbnail, the 34nm 32 Gb chip will cost-effectively enable high-density solid-state storage in small form factor applications.
A single 32 Gb chip could store more than 2,000 high-resolution digital photos or hold up to 1,000 songs on a personal music player.
Two 8-die stacked packages would realize 64 gigabytes (GBs) of storage, enough for recording anywhere from eight to 40 hours of high-definition video in a digital camcorder.
The 34nm 32Gb chip was designed with solid-state drives in mind. The product will enable more cost-effective SSDs, instantly doubling the current storage volume of these devices and driving capacities to beyond 256 GBs in today’s standard, smaller 1.8-inch form factor. SSDs are becoming the new storage medium for notebook computers, providing lower power, faster boot-up time, increased reliability, improved performance and reduced noise than hard disk drives. With the innovations in NAND process technology, such as with the 34nm NAND process, SSDs now offer a significant range of capacities to meet market requirements.
Based on the 34nm architecture, Intel and Micron also plan to introduce lower density multi-level cell products including single-level cell products, by the end of this calendar year.
About Intel
Intel (NASDAQ: INTC), the world leader in silicon innovation, develops technologies, products and initiatives to continually advance how people work and live. Additional information about Intel is available at www.intel.com/pressroom and http://blogs.intel.com. For more details on Intel NAND flash products go to www.intel.com/design/flash/nand.
About Micron
Micron Technology, Inc., is one of the world's leading providers of advanced semiconductor solutions. Through its worldwide operations, Micron manufactures and markets DRAMs, NAND flash memory, CMOS image sensors, other semiconductor components, and memory modules for use in leading-edge computing, consumer, networking, and mobile products. Micron’s common stock is traded on the New York Stock Exchange (NYSE) under the MU symbol. To learn more about Micron Technology, Inc., visit www.micron.com.
©2008 Micron Technology, Inc., and Intel Corporation. All rights reserved. Information is subject to change without notice.
Micron and the Micron logo are trademarks of Micron Technology, Inc. Intel is a trademark of Intel Corporation in the United States and other countries. All other trademarks are the property of their respective owners.
This press release contains forward-looking statements regarding the production of the 34nm 32 Gb NAND device. Actual events or results may differ materially from those contained in the forward-looking statements. Please refer to the documents the Company files on a consolidated basis from time to time with the Securities and Exchange Commission, specifically the Company's most recent Form 10-K and Form 10-Q. These documents contain and identify important factors that could cause the actual results for the Company on a consolidated basis to differ materially from those contained in our forward-looking statements (see Certain Factors). Although we believe that the expectations reflected in the forward-looking statements are reasonable, we cannot guarantee future results, levels of activity, performance or achievements.
Boise, Idaho and Santa Clara, Calif. , Thursday, May 29, 2008 – Today Intel Corporation and Micron Technology, Inc. introduced the industry’s first sub-40 nanometer (nm) NAND memory device, unveiling a 34nm 32 gigabit (Gb) multi-level cell chip. This process technology was jointly developed by Intel and Micron and manufactured by the companies’ NAND flash joint venture, IM Flash Technologies (IMFT). It is the smallest NAND process geometry on the market. The 32 Gb NAND chip is the only monolithic device at this density that fits into a standard 48-lead thin small-outline package (TSOP), providing a cost-effective path to higher densities in existing applications. Shipments of customer samples begin in June and mass production is expected during the second half of this calendar year.
“This new 32 Gb device provides the best bit storage density available in the industry,” said Brian Shirley, vice president of Micron’s Memory Group. “Together with our partners at Intel, we’re proud to have now taken the lead in production process technology.”
“The introduction of 34nm process technology highlights IMFT’s rapid progress and moves us to the forefront of NAND process technology,” said Pete Hazen, director of marketing, Intel NAND Products Group. “These advancements will expand the value proposition and accelerate the adoption of solid-state drive (SSD) solutions in computing platforms.”
The 34nm 32 Gb chips will be manufactured on 300 millimeter wafers, each producing approximately 1.6 terabytes of NAND. Measuring just 172mm², less than the size of a thumbnail, the 34nm 32 Gb chip will cost-effectively enable high-density solid-state storage in small form factor applications.
A single 32 Gb chip could store more than 2,000 high-resolution digital photos or hold up to 1,000 songs on a personal music player.
Two 8-die stacked packages would realize 64 gigabytes (GBs) of storage, enough for recording anywhere from eight to 40 hours of high-definition video in a digital camcorder.
The 34nm 32Gb chip was designed with solid-state drives in mind. The product will enable more cost-effective SSDs, instantly doubling the current storage volume of these devices and driving capacities to beyond 256 GBs in today’s standard, smaller 1.8-inch form factor. SSDs are becoming the new storage medium for notebook computers, providing lower power, faster boot-up time, increased reliability, improved performance and reduced noise than hard disk drives. With the innovations in NAND process technology, such as with the 34nm NAND process, SSDs now offer a significant range of capacities to meet market requirements.
Based on the 34nm architecture, Intel and Micron also plan to introduce lower density multi-level cell products including single-level cell products, by the end of this calendar year.
About Intel
Intel (NASDAQ: INTC), the world leader in silicon innovation, develops technologies, products and initiatives to continually advance how people work and live. Additional information about Intel is available at www.intel.com/pressroom and http://blogs.intel.com. For more details on Intel NAND flash products go to www.intel.com/design/flash/nand.
About Micron
Micron Technology, Inc., is one of the world's leading providers of advanced semiconductor solutions. Through its worldwide operations, Micron manufactures and markets DRAMs, NAND flash memory, CMOS image sensors, other semiconductor components, and memory modules for use in leading-edge computing, consumer, networking, and mobile products. Micron’s common stock is traded on the New York Stock Exchange (NYSE) under the MU symbol. To learn more about Micron Technology, Inc., visit www.micron.com.
©2008 Micron Technology, Inc., and Intel Corporation. All rights reserved. Information is subject to change without notice.
Micron and the Micron logo are trademarks of Micron Technology, Inc. Intel is a trademark of Intel Corporation in the United States and other countries. All other trademarks are the property of their respective owners.
This press release contains forward-looking statements regarding the production of the 34nm 32 Gb NAND device. Actual events or results may differ materially from those contained in the forward-looking statements. Please refer to the documents the Company files on a consolidated basis from time to time with the Securities and Exchange Commission, specifically the Company's most recent Form 10-K and Form 10-Q. These documents contain and identify important factors that could cause the actual results for the Company on a consolidated basis to differ materially from those contained in our forward-looking statements (see Certain Factors). Although we believe that the expectations reflected in the forward-looking statements are reasonable, we cannot guarantee future results, levels of activity, performance or achievements.
AMD slashes $880M from value of division
SAN JOSE, Calif. - Struggling to climb back to profitability, Advanced Micro Devices Inc. suffered another setback Friday when the chip maker disclosed that two businesses it acquired in a pricey acquisition were underperforming.
AMD said the businesses' values would have to be reduced by $880 million. It's the second time AMD has had to slash the value of businesses it absorbed as part of its pricey — and controversial — acquisition of graphics chip maker ATI Technologies Inc.
Shares in AMD fell 12 cents, or 2.4 percent, to $4.84 Friday, after earlier changing hands at $4.60, their lowest point since October 2002.
Sunnyvale-based AMD is the world's No. 2 maker of microprocessors, the brains of personal computers.
AMD and its much-larger rival, Intel Corp., are both pushing deeper into graphics technologies, typically handled on separate chips, as the demand intensifies on computers to render better graphics for Internet video, computer games and high-definition movies.
Santa Clara-based Intel has chosen to beef up the graphics capabilities of its chips in-house, while AMD decided to buy its way in with the $5.6 billion acquisition of ATI in October 2006, a decision that is still hurting the company financially.
AMD is now the world's second-largest maker of standalone graphics chips, behind Santa Clara-based Nvidia Corp.
In a filing with the Securities and Exchange Commission, AMD said it recently discovered that its business units that make chips for cell phones and digital televisions, both acquired as part of the ATI transaction and considered "noncore" parts of AMD's operations, weren't performing up to expectations.
As a result, the company plans to write down the value of their goodwill, or intangible assets such as reputation, and take charges of $880 million in the latest quarter, which ended June 28.
AMD had previously written down ATI's overall value by $1.6 billion in January, in a staggering reassessment that indicated the perception of ATI in the market had slipped dramatically.
Taken together, AMD has effectively said that ATI is now worth 44 percent less as a company than when AMD bought it.
Investors have punished AMD's stock as they await word about the company's plans to sell off slumping business units or even some of its factories, a huge expense for semiconductor companies. More details could emerge Thursday when AMD reports financial results for the second quarter.
AMD was flying high just two years ago, with a stock near $40 a share in February 2006, as AMD was stealing substantial market share from Intel in the lucrative server business, a market AMD didn't enter until 2003. But its fortunes have faded since then on investors' concerns about the company's huge losses and faltering competitive position.
AMD has racked up more than $4 billion in losses over the last year and a half as competition from Intel intensifies and AMD struggles to recover from its own product delays.
AMD also said Friday that it plans to take a $32 million restructuring charge in the latest quarter, mostly for employee severance payments. The company plans to cut 10 percent of its global work force, or about 1,600 workers, by September.
AMD is also writing down $36 million in the value of its short-term investments in the latest quarter, stemming from its stake in Spansion Inc., which makes flash memory chips, and holdings in auction rate securities.
Meanwhile, the company expects to record a gain of $190 million from the sale of some chip-making equipment.
AMD said the businesses' values would have to be reduced by $880 million. It's the second time AMD has had to slash the value of businesses it absorbed as part of its pricey — and controversial — acquisition of graphics chip maker ATI Technologies Inc.
Shares in AMD fell 12 cents, or 2.4 percent, to $4.84 Friday, after earlier changing hands at $4.60, their lowest point since October 2002.
Sunnyvale-based AMD is the world's No. 2 maker of microprocessors, the brains of personal computers.
AMD and its much-larger rival, Intel Corp., are both pushing deeper into graphics technologies, typically handled on separate chips, as the demand intensifies on computers to render better graphics for Internet video, computer games and high-definition movies.
Santa Clara-based Intel has chosen to beef up the graphics capabilities of its chips in-house, while AMD decided to buy its way in with the $5.6 billion acquisition of ATI in October 2006, a decision that is still hurting the company financially.
AMD is now the world's second-largest maker of standalone graphics chips, behind Santa Clara-based Nvidia Corp.
In a filing with the Securities and Exchange Commission, AMD said it recently discovered that its business units that make chips for cell phones and digital televisions, both acquired as part of the ATI transaction and considered "noncore" parts of AMD's operations, weren't performing up to expectations.
As a result, the company plans to write down the value of their goodwill, or intangible assets such as reputation, and take charges of $880 million in the latest quarter, which ended June 28.
AMD had previously written down ATI's overall value by $1.6 billion in January, in a staggering reassessment that indicated the perception of ATI in the market had slipped dramatically.
Taken together, AMD has effectively said that ATI is now worth 44 percent less as a company than when AMD bought it.
Investors have punished AMD's stock as they await word about the company's plans to sell off slumping business units or even some of its factories, a huge expense for semiconductor companies. More details could emerge Thursday when AMD reports financial results for the second quarter.
AMD was flying high just two years ago, with a stock near $40 a share in February 2006, as AMD was stealing substantial market share from Intel in the lucrative server business, a market AMD didn't enter until 2003. But its fortunes have faded since then on investors' concerns about the company's huge losses and faltering competitive position.
AMD has racked up more than $4 billion in losses over the last year and a half as competition from Intel intensifies and AMD struggles to recover from its own product delays.
AMD also said Friday that it plans to take a $32 million restructuring charge in the latest quarter, mostly for employee severance payments. The company plans to cut 10 percent of its global work force, or about 1,600 workers, by September.
AMD is also writing down $36 million in the value of its short-term investments in the latest quarter, stemming from its stake in Spansion Inc., which makes flash memory chips, and holdings in auction rate securities.
Meanwhile, the company expects to record a gain of $190 million from the sale of some chip-making equipment.
Samsung rumors pour cold water on Semicon
SAN FRANCISCO — Rumors that Samsung Electronics Co. Ltd. this week pushed out its fab-tool orders sent shock waves at the Semicon West trade show here, putting vendors in a somber and gloomy mood. The chain of events also prompted many to predict an acceleration of the current shakeout taking place in the fab-tool arena.
The semiconductor-equipment market was already in the midst of a slowdown amid what some call a ''disconnect'' in the sector. Fab utilization rates remain high, but capital spending is down by some 20-to-25 percent due to a lull in ICs.
Compounding the ''disconnect'' at Semicon West is a solar event, which is running in tandem at the show. While there is a buzz at the Intersolar event, the semiconductor fab-tool portion of the show is relatively quiet, with vendors grumbling about the lack of foot traffic in their booths.
Reports that Samsung is now putting the brakes on its capital spending exacerbated the doom-and-gloom sentiment. Samsung is the world's largest buyer of capital equipment, surpassing Intel Corp. several years ago, it was noted.
Amid the Samsung rumors, many are beginning to whisper the ''D'' word: downturn. Still others say it's much worse and calling it a depression.
The net effect: Expect an acceleration of the ongoing shakeout in the fab-tool and electronics materials industries. The strong will get stronger and the weak will not survive over the long haul.
Which companies are the next takeover targets? Axcelis, ASMI and Asyst are currently fending off unfriendly takeover bids. Perhaps some big-name players--Lam, Novellus and Varian--are in play. Most certainty, the new startups will be the first takeover targets.
Clearly, the landscape will change--again. Indeed, the current outlook reminds many of the severe and deep downturn in 2001. The semiconductor-equipment market is projected to hit $34.12 billion in 2008, down 20 percent over 2007, according to SEMI.
In comparison, the fab-tool market grew by 6 percent in 2007, according to SEMI (San Jose, Calif.). Following the downturn in 2008, the semiconductor-equipment market is projected to rebound with annual growth of 13 percent and 6 percent in 2009 and 2010, respectively, according to the trade group.
The poor climate in 2008 is due to ''lower spending in the memory sector and a less than favorable device pricing environment,'' said Stanley Myers, president and CEO, of SEMI at a press event.
Capital spending in the memory sector is especially troublesome, said Rick Hill, president and chief executive of Novellus Systems Inc. (San Jose, Calif.) "No one can argue that memory is under pressure,'' Hill said during the company's analyst meeting. "Do I think the market will get better when I wake up in the morning? Hell no. I need Maalox every morning.''
In addition to the business woes, the U.S. sub-prime mortgage crisis and soaring oil prices ''creates uncertainties'' in the overall economy, thereby impacting consumer spending for electronic goods, said Harvey Frye, president of Tokyo Electron America Inc. (Austin, Texas). Tokyo Electron America is the U.S. subsidiary of Japanese semiconductor equipment giant Tokyo Electron Ltd. (TEL).
A poor memory environment, coupled with economic woes, spells bad news for vendors. ''This is a big downturn," declared Mike Splinter, president and CEO of Applied Materials Inc. (Santa Clara, Calif.), at the company's analyst meeting.
Overall, semiconductor equipment is a ''tough market," he said. Originally, Applied projected that the front-end equipment market would fall by 5-to-15 percent in 2008 over 2007. Now, the world's largest equipment vendor projects that the wafer-fab equipment segment could fall bt 25-to-30 percent this year, he said.
On the bright side, flat-panel displays are still growing and capital spending could jump by 30 percent in 208. "Capex has been bigger than what we expected,'' he said.
Applied, which has made a number of acquisitions in the solar-gear market, also sees strong growth in that business. The company ''has not caught up'' with demand for solar gear, he added.
2009 forecast
Going forward, some see a slight recovery in 2009. Others see a prolonged downturn.
Much of the recovery hinges on the memory market. But a recovery ''is hard to predict,'' said Brian Trafas, chief marketing officer at KLA-Tencor Corp. (San Jose, Calif.). "Until we see an uptick in memory pricing, it's hard to see any capacity buys.''
"2009 looks like a flattish year," said Jerry Cutini, president and CEO of Aviza Technology Inc. (Scotts Valley, Calif.) ''Flat would be considered good in 2009.''
2009 could take a turn for the worse--if, say, oil prices continue to soar. "If oil goes to $200 a barrel, it's going to be a bad year,'' he said.
During a presentation, Tom St. Dennis, senior vice president and general manager of the Silicon Systems Group at Applied Materials, listed several drivers that could bring the industry out of its slump. Among the major drivers are DDR3 memory, solid-state storage drives, and next-generation communications and graphics chips, he said.
What is clear that the landscape will change in semiconductor equipment. For example, no less than three vendors are fighting off hostile takeovers.
Applied's Splinter recently reiterated that its offer to buy part of ASM International (Bilthoven, the Netherlands) was "full and fair." Late last month, ASMI rejected the unsolicited offer from Applied Materials and private-equity firm Francisco Partners to acquire all of ASMI's front-end businesses for up to $800 million.
Chip-equipment maker Axcelis Technologies Inc. (Beverly, Mass.) said that the company, Japan's Sumitomo Heavy Industries Ltd. (SHI) and private-equity firm TPG Capital have entered into a ''confidentiality agreement'' with respect to discussions between the parties. The companies did not elaborate, but for some time, SHI and TPG have made various unsolicited offers to acquire Axcelis.
Contrary to popular belief, Aquest Systems Corp. has not given up on its efforts to acquire Asyst Technologies Inc. Fab-tool automation firm Asyst recently announced that it had received notice from Riley Investment Partners Master Fund L.P., a hedge fund that with related parties claims to own 2.6 percent of Asyst's outstanding shares.
Riley intends to nominate six directors for election at the company's 2008 annual meeting in an attempt to gain control of Asyst's board. Riley's notice stated that its nominees, if elected, intend to sell the company through an auction process.
Adding to the intrigue, Aquest is an investor in Riley, said Mihir Parikh, president and CEO of Aquest. Parikh was also the founder of Asyst and its CEO from its inception in 1984 until 2002. And if or when Asyst goes up for sale, Aquest will be one of the bidders, he said.
The semiconductor-equipment market was already in the midst of a slowdown amid what some call a ''disconnect'' in the sector. Fab utilization rates remain high, but capital spending is down by some 20-to-25 percent due to a lull in ICs.
Compounding the ''disconnect'' at Semicon West is a solar event, which is running in tandem at the show. While there is a buzz at the Intersolar event, the semiconductor fab-tool portion of the show is relatively quiet, with vendors grumbling about the lack of foot traffic in their booths.
Reports that Samsung is now putting the brakes on its capital spending exacerbated the doom-and-gloom sentiment. Samsung is the world's largest buyer of capital equipment, surpassing Intel Corp. several years ago, it was noted.
Amid the Samsung rumors, many are beginning to whisper the ''D'' word: downturn. Still others say it's much worse and calling it a depression.
The net effect: Expect an acceleration of the ongoing shakeout in the fab-tool and electronics materials industries. The strong will get stronger and the weak will not survive over the long haul.
Which companies are the next takeover targets? Axcelis, ASMI and Asyst are currently fending off unfriendly takeover bids. Perhaps some big-name players--Lam, Novellus and Varian--are in play. Most certainty, the new startups will be the first takeover targets.
Clearly, the landscape will change--again. Indeed, the current outlook reminds many of the severe and deep downturn in 2001. The semiconductor-equipment market is projected to hit $34.12 billion in 2008, down 20 percent over 2007, according to SEMI.
In comparison, the fab-tool market grew by 6 percent in 2007, according to SEMI (San Jose, Calif.). Following the downturn in 2008, the semiconductor-equipment market is projected to rebound with annual growth of 13 percent and 6 percent in 2009 and 2010, respectively, according to the trade group.
The poor climate in 2008 is due to ''lower spending in the memory sector and a less than favorable device pricing environment,'' said Stanley Myers, president and CEO, of SEMI at a press event.
Capital spending in the memory sector is especially troublesome, said Rick Hill, president and chief executive of Novellus Systems Inc. (San Jose, Calif.) "No one can argue that memory is under pressure,'' Hill said during the company's analyst meeting. "Do I think the market will get better when I wake up in the morning? Hell no. I need Maalox every morning.''
In addition to the business woes, the U.S. sub-prime mortgage crisis and soaring oil prices ''creates uncertainties'' in the overall economy, thereby impacting consumer spending for electronic goods, said Harvey Frye, president of Tokyo Electron America Inc. (Austin, Texas). Tokyo Electron America is the U.S. subsidiary of Japanese semiconductor equipment giant Tokyo Electron Ltd. (TEL).
A poor memory environment, coupled with economic woes, spells bad news for vendors. ''This is a big downturn," declared Mike Splinter, president and CEO of Applied Materials Inc. (Santa Clara, Calif.), at the company's analyst meeting.
Overall, semiconductor equipment is a ''tough market," he said. Originally, Applied projected that the front-end equipment market would fall by 5-to-15 percent in 2008 over 2007. Now, the world's largest equipment vendor projects that the wafer-fab equipment segment could fall bt 25-to-30 percent this year, he said.
On the bright side, flat-panel displays are still growing and capital spending could jump by 30 percent in 208. "Capex has been bigger than what we expected,'' he said.
Applied, which has made a number of acquisitions in the solar-gear market, also sees strong growth in that business. The company ''has not caught up'' with demand for solar gear, he added.
2009 forecast
Going forward, some see a slight recovery in 2009. Others see a prolonged downturn.
Much of the recovery hinges on the memory market. But a recovery ''is hard to predict,'' said Brian Trafas, chief marketing officer at KLA-Tencor Corp. (San Jose, Calif.). "Until we see an uptick in memory pricing, it's hard to see any capacity buys.''
"2009 looks like a flattish year," said Jerry Cutini, president and CEO of Aviza Technology Inc. (Scotts Valley, Calif.) ''Flat would be considered good in 2009.''
2009 could take a turn for the worse--if, say, oil prices continue to soar. "If oil goes to $200 a barrel, it's going to be a bad year,'' he said.
During a presentation, Tom St. Dennis, senior vice president and general manager of the Silicon Systems Group at Applied Materials, listed several drivers that could bring the industry out of its slump. Among the major drivers are DDR3 memory, solid-state storage drives, and next-generation communications and graphics chips, he said.
What is clear that the landscape will change in semiconductor equipment. For example, no less than three vendors are fighting off hostile takeovers.
Applied's Splinter recently reiterated that its offer to buy part of ASM International (Bilthoven, the Netherlands) was "full and fair." Late last month, ASMI rejected the unsolicited offer from Applied Materials and private-equity firm Francisco Partners to acquire all of ASMI's front-end businesses for up to $800 million.
Chip-equipment maker Axcelis Technologies Inc. (Beverly, Mass.) said that the company, Japan's Sumitomo Heavy Industries Ltd. (SHI) and private-equity firm TPG Capital have entered into a ''confidentiality agreement'' with respect to discussions between the parties. The companies did not elaborate, but for some time, SHI and TPG have made various unsolicited offers to acquire Axcelis.
Contrary to popular belief, Aquest Systems Corp. has not given up on its efforts to acquire Asyst Technologies Inc. Fab-tool automation firm Asyst recently announced that it had received notice from Riley Investment Partners Master Fund L.P., a hedge fund that with related parties claims to own 2.6 percent of Asyst's outstanding shares.
Riley intends to nominate six directors for election at the company's 2008 annual meeting in an attempt to gain control of Asyst's board. Riley's notice stated that its nominees, if elected, intend to sell the company through an auction process.
Adding to the intrigue, Aquest is an investor in Riley, said Mihir Parikh, president and CEO of Aquest. Parikh was also the founder of Asyst and its CEO from its inception in 1984 until 2002. And if or when Asyst goes up for sale, Aquest will be one of the bidders, he said.
Achieve PCIe compliance and interoperability in your IP core-based design
Since its inception more than five years ago, PCIe technology has become the dominant interconnect protocol across virtually all market segments. Today, all of the major chipset vendors are implementing PCIe technology into their chipsets.
The quick adoption of PCIe technology has resulted in a market flooded with many different implementations of the PCIe specification. While, theoretically, each of these implementations should be compliant with the specification and interoperate with all other implementations, the reality is that non-compliant and non-interoperable devices do make their way to the marketplace.
When one considers the high cost of fixing a non-compliant or non-interoperable device once it reaches silicon, much less once it has been released to the market, assuring pre-silicon compliance and interoperability of a device becomes one of the most important challenges to any PCIe development process.
Recognizing this enormous cost, the EDA industry has come forth with a myriad of solutions capable of managing this obstacle. These solutions include advanced verification and assertion languages, functional coverage tools, and protocol specific models and compliance test suites.
Given the wide range of solutions made available by the EDA industry, selecting the best solution to assure pre-silicon compliance and interoperability of a device requires a thorough understanding of the issues that cause devices to be deemed noncompliant or non-interoperable.
Challenges
As one reads the PCIe Base Specification, or any specification for that matter, assumptions are made as to how the device is intended to behave.
Although standards bodies such as the PCI-Special Interest Group (SIG) take great strides to remove all ambiguity from their specifications, these specifications remain open to interpretation, and assumptions are made as developers read the specification.
In the best-case scenario, these assumptions are consistent amongst developers and with the intent of the author of the specification, whom in this case is the PCI-SIG. In reality, this consistency is often absent. More commonly, differing assumptions exist between developers.
In this case, the resolution of these differences comes only after extensive discussions, which oftentimes require the guidance of the author of the specification.
In the worst-case scenario, all developers make the same assumptions, which are, unfortunately, inconsistent with the intent of the author of the specification. In this case, the resulting device does not match the intent of the specification.
Therefore, it is critical for any pre-silicon compliance solution to have identified and resolved all assumptions made in the development of the said solution.
Assumptions are identified and resolved as more developers review and use the solution. The result is that as a solution gains wider acceptance in the industry, more confidence can be placed in the accuracy of the solution.
As devices continue to grow in size and complexity, the task of enumerating, much less verifying, all possible scenarios becomes extremely difficult. And it becomes increasingly probable that some features of the device will not be covered in the verification process.
Although the PCIe specification details hundreds of registers, multiple complex state machines and a plethora of optional functionality, this is not an issue unique to the PCIe specification.
In response to this industry-wide issue, coverage-driven verification methodologies have been developed and successfully proven. These methodologies generally involve the placement of assertions into the device and the verification environment.
Once the assertions are placed, random stimulus is applied to the device, and coverage statistics are collected. As such, to be useful in a coverage-driven verification methodology, any pre-silicon compliance solution must include a robust set of assertions, along with a facility for the collection of coverage statistics.
Verifying IP cores
With the rapid adoption of PCIe technology, PCIe design cores are quickly becoming commodity parts. Generally, there is little value to be added to a device by building a PCIe design core from scratch when a wide variety of PCIe design cores are available from many vendors, each offering its own set of features.
Ideally, all PCIe design cores on the market should be bug-free; however, that is not always the case. Therefore, the challenge for any development team using a PCIe design core is to determine how to deal with a core that has presumably been verified.
Most development teams either do not have or do not wish to allocate resources to the verification of a pre-verified PCIe design core.
As such, a presilicon compliance solution that provides a complete, self-contained verification environment is instrumental in filling this gap, provided the solution can be easily integrated with the device.
Additionally, given the limited resources generally applied to this task, any issues identified by the solution must be easily debugged and resolved.
Interoperability testing
Interoperability is defined as the ability of a device to communicate with all other devices. In the PCIe domain, this implies that two devices are interoperable if, and only if, the devices can correctly manage their connection and exchange transactions.
For a device to be fully interoperable, it must be able to do this with all possible devices on the market. Interoperability in a pre-silicon environment is extremely difficult. Indirect interoperability is an alternative option.
The concept of indirect interoperability states that, given three devices, if the first two devices are known to interoperate with the third device, then the first two should be interoperable with each other (Figure 1, above ).
Applying this concept, a pre-silicon compliance solution provides an assurance that the device will be interoperable with all other devices using the same solution (Figure 2 below).
As a given solution gains wider acceptance throughout the industry and is used to assure pre-silicon compliance with a wider array of devices, this wider array of devices will be known to interoperate with each other.
As the cost of a silicon re-spin grows with each passing day, it becomes critical to assure pre-silicon compliance and interoperability for all PCIe devices. The sources of compliance and interoperability bugs are complex and often go unnoticed.
The only way to mitigate the risk of producing a non-compliant or non-interoperable device is to address each of these sources with a widely accepted and easily integrated solution containing advanced verification features.
Joshua Filliater is an Applications Engineer at Denali Software, Inc.
The quick adoption of PCIe technology has resulted in a market flooded with many different implementations of the PCIe specification. While, theoretically, each of these implementations should be compliant with the specification and interoperate with all other implementations, the reality is that non-compliant and non-interoperable devices do make their way to the marketplace.
When one considers the high cost of fixing a non-compliant or non-interoperable device once it reaches silicon, much less once it has been released to the market, assuring pre-silicon compliance and interoperability of a device becomes one of the most important challenges to any PCIe development process.
Recognizing this enormous cost, the EDA industry has come forth with a myriad of solutions capable of managing this obstacle. These solutions include advanced verification and assertion languages, functional coverage tools, and protocol specific models and compliance test suites.
Given the wide range of solutions made available by the EDA industry, selecting the best solution to assure pre-silicon compliance and interoperability of a device requires a thorough understanding of the issues that cause devices to be deemed noncompliant or non-interoperable.
Challenges
As one reads the PCIe Base Specification, or any specification for that matter, assumptions are made as to how the device is intended to behave.
Although standards bodies such as the PCI-Special Interest Group (SIG) take great strides to remove all ambiguity from their specifications, these specifications remain open to interpretation, and assumptions are made as developers read the specification.
In the best-case scenario, these assumptions are consistent amongst developers and with the intent of the author of the specification, whom in this case is the PCI-SIG. In reality, this consistency is often absent. More commonly, differing assumptions exist between developers.
In this case, the resolution of these differences comes only after extensive discussions, which oftentimes require the guidance of the author of the specification.
In the worst-case scenario, all developers make the same assumptions, which are, unfortunately, inconsistent with the intent of the author of the specification. In this case, the resulting device does not match the intent of the specification.
Therefore, it is critical for any pre-silicon compliance solution to have identified and resolved all assumptions made in the development of the said solution.
Assumptions are identified and resolved as more developers review and use the solution. The result is that as a solution gains wider acceptance in the industry, more confidence can be placed in the accuracy of the solution.
As devices continue to grow in size and complexity, the task of enumerating, much less verifying, all possible scenarios becomes extremely difficult. And it becomes increasingly probable that some features of the device will not be covered in the verification process.
Although the PCIe specification details hundreds of registers, multiple complex state machines and a plethora of optional functionality, this is not an issue unique to the PCIe specification.
In response to this industry-wide issue, coverage-driven verification methodologies have been developed and successfully proven. These methodologies generally involve the placement of assertions into the device and the verification environment.
Once the assertions are placed, random stimulus is applied to the device, and coverage statistics are collected. As such, to be useful in a coverage-driven verification methodology, any pre-silicon compliance solution must include a robust set of assertions, along with a facility for the collection of coverage statistics.
Verifying IP cores
With the rapid adoption of PCIe technology, PCIe design cores are quickly becoming commodity parts. Generally, there is little value to be added to a device by building a PCIe design core from scratch when a wide variety of PCIe design cores are available from many vendors, each offering its own set of features.
Ideally, all PCIe design cores on the market should be bug-free; however, that is not always the case. Therefore, the challenge for any development team using a PCIe design core is to determine how to deal with a core that has presumably been verified.
Most development teams either do not have or do not wish to allocate resources to the verification of a pre-verified PCIe design core.
As such, a presilicon compliance solution that provides a complete, self-contained verification environment is instrumental in filling this gap, provided the solution can be easily integrated with the device.
Additionally, given the limited resources generally applied to this task, any issues identified by the solution must be easily debugged and resolved.
Interoperability testing
Interoperability is defined as the ability of a device to communicate with all other devices. In the PCIe domain, this implies that two devices are interoperable if, and only if, the devices can correctly manage their connection and exchange transactions.
For a device to be fully interoperable, it must be able to do this with all possible devices on the market. Interoperability in a pre-silicon environment is extremely difficult. Indirect interoperability is an alternative option.
The concept of indirect interoperability states that, given three devices, if the first two devices are known to interoperate with the third device, then the first two should be interoperable with each other (Figure 1, above ).
Applying this concept, a pre-silicon compliance solution provides an assurance that the device will be interoperable with all other devices using the same solution (Figure 2 below).
As a given solution gains wider acceptance throughout the industry and is used to assure pre-silicon compliance with a wider array of devices, this wider array of devices will be known to interoperate with each other.
As the cost of a silicon re-spin grows with each passing day, it becomes critical to assure pre-silicon compliance and interoperability for all PCIe devices. The sources of compliance and interoperability bugs are complex and often go unnoticed.
The only way to mitigate the risk of producing a non-compliant or non-interoperable device is to address each of these sources with a widely accepted and easily integrated solution containing advanced verification features.
Joshua Filliater is an Applications Engineer at Denali Software, Inc.
Low power design for analog/mixed signal IP
Power reduction and management techniques using multiple clock and power domains, dynamic voltage and frequency scaling and power gating are effective for digital circuits but for analog design, lowering power consumption must be considered early in the design phase. Starting with the techniques for lowering the power consumption in analog circuits such as operational amplifiers, this article will then focus on low power design for high-speed serial interconnects. Different architectures for output drivers and methods such as level shifting, for ac-coupled systems such as PCIe, Serial ATA and XAUI will be discussed.
System designers are influencing the specifications of high speed serial interconnects and a good example of this can be seen with the emerging standards for the USB protocol: LPM and HSIC. USB is prevalent as the high-speed serial interconnect in portable devices such as smart phones and mobile Internet devices. The goal of link power management (LPM) is to reduce power consumption of USB devices and hosts, potentially extending battery life by at least 20 percent. HSIC or "high speed inter-chip USB" allows low power high-speed data transfers (480Mbit/s) using a source synchronous clocked serial interface. Both will be reviewed in this article.
Back to basics: The op amp
In the design of analog/mixed-signal IP many factors contribute to the overall consumption of power. The common methods include:
Simplifying the complexity of the circuit and using folded designs exploiting the complementary properties of NMOS and PMOS devices.
Taking conventional architectures and converting them into designs that consume less power with adaptive biasing.
Gearing the integrated circuit technology towards low power performance by using high Vt processes for example 65nm LP or 40nm LP. Although this may not necessarily reduce power in the active mode as more current is needed to drive the high-speed transmitter in the slower, low power technologies.
Decreasing transistor dimensions together with lowering the supply voltage.
Before delving into power reduction techniques for high speed serial interfaces, consider the case of an operational amplifier as the techniques applied here are pertinent to many other circuit examples.
1. The power consumption of the operational amplifier can be reduced by use of an architecture with only a single (differential) stage. This will reduce the current consumption of the device. However, a method of maximizing the gain, while preserving an acceptable bandwidth and slew rate are now required in the single gain stage.
2. The output stage could be designed to provide sufficient output drive while quiescently consuming as little power as possible.
3. Optimizing the biasing circuit will reduce the power consumption in the op-amp. This is achieved by reducing the internal stage currents by programming an external current in the form of a resistor outside the integrated circuit. Speed, voltage noise and junction leakage will now become major considerations for the designer as these parameters are affected by the value of the bias current programmed.
4. Two important factors that determine the maximum power dissipation in an integrated circuit are the technology used for the design and the type of application. A particular application for CMOS op-amps could be low power switched capacitor filters. If a lower power/low leakage CMOS technology such as 65LP or 40LP is used, then there are two important requirements in the op-amp design. First there must be enough current to charge the compensation capacitor and load capacitor in the required time. Second there must be enough current in the second gain stage transistor to maintain a phase margin of 45 to avoid ringing and degradation of the settling time. If the output current of this circuit is less than the quiescent bias current then this is known as a Class A circuit.
5. Quiescent power dissipation can be reduced by replacing Class A op-amps with Class AB and dynamic op-amps. The Class AB output stage is designed to be biased at small currents so quiescent power dissipation is correspondingly lower.
6. The basic two-stage differential input op-amp can be designed in the sub-threshold current region to minimize the current consumption.
Scaling issues: Is analog anti-Moore?
Whereas scaling of digital circuits is has been investigated in detail, the application of scaling analog circuits is still not that common. For example typical transistor dimensions in an analog circuit are a few multiples larger than 40nm minimum channels.
The sub-threshold characteristics of devices with channel lengths below 2m are very different to devices with larger dimensions. It has been observed that the current becomes exponentially dependent on drain voltage independent of VDS. This effect is sometimes referred to as "drain induced barrier lowering" (DIBL). If this effect can be avoided then IDdecreases exponentially as VGS is reduced below VT.
Scaling devices, and reducing the supply voltage accordingly, will not degrade open circuit voltage gain. Scaling dimensions but keeping supply voltage constant will, however, decrease the gain. The dynamic range of circuits such as op-amps fall because the analog signal range becomes limited due to the reduction in the power supply voltage. The problems of scaling down include fabrication challenges, limitations in the design of devices and circuits and the efficiency and distribution of power supplies.
Thermal noise will remain constant because the device transconductance remains constant under constant field scaling. The 1/f noise intensifies, but the effect of this can be reduced by translating the signal to a higher portion of the frequency spectrum, using chopper stabilization.
Low power guidelines
A set of guidelines can be developed for low power analog design, considering the op-amp as an example: the biasing circuitry, input, output and compensation stages can be examined.
The DC biasing circuitry for the op-amp must provide accurately determined and suitably regulated quiescent biasing currents at very low current levels. The current must be insensitive to changes in temperature, supply voltage and process tolerances.
The configuration of the input stage will dictate whether the op-amp can be used in a single low voltage (1.2V, or lower) supply application. Therefore the following properties are desirable (but not always possible) on a particular low power analog design:
Very low power supply operation using core devices Class B or AB output stage " this reduces the quiescent power dissipation particularly in a leaky process A rail to rail common mode input range A load-capacitance aware compensation scheme Capability to drive a small output load Bandwidth and slew rate commensurate with supply current Getting high precision by keeping offsets low, high input impedance, high CMRR and high PSRR.
Low power design example
The following is an example of a low-power, high-speed driver used in a USB 2.0 PHY. Power is kept very low with the use of a voltage-mode driver, shown in Figure 1.
In fact, for AC-coupled systems such as PCIe, Serial ATA and XAUI, a voltage-mode driver draws 25 percent of the supply current of a current-mode implementation. For example, a classical USB 2.0 driver requires nominal amplitude of 400mV for high-speed data transmission into a 45 load. The static power dissipation from the supply for a current-mode driver is approximately 60mW. Whereas, the power dissipation from the supply for a voltage-mode driver is approximately 30mW.
Another power-reduction technique is to optimize by level shifting down into the low-voltage core device domain as early as possible in the signal path so that device characteristics are leveraged as much as possible in order to reduce power. This strategy enables most high-frequency analog signal processing to be done in the low-voltage domain (for example in the USB, high-speed squelch detection and high speed receive function are implemented using low voltage core devices).
Low-power design is also important in sleep modes (non-functional modes) especially for mobile devices. For example, in the USB protocol the PHY can be held in suspend mode for long periods of time. As a result the power dissipation in this mode can become a significant portion of the total and must be scaled aggressively.
Power gating in digital circuits is often used where more aggressive power reduction is necessary. Power gating helps reduce both channel and gate leakage by collapsing the supply and eliminating the leakage current path. This can be implemented on a sub-block level by implementing collapsible, thick-oxide regulators that can be disabled in low-power modes.
Digital supply leakage often dominates the power down current and so many SoC's collapse the digital (core) supply rail in these modes as well. Doing so can cause serious side effects as analog level-shifters found in MSIP can often cause excessive current draw. Special care in the design of level shifters found in MSIP is necessary to avoid this. One example includes circuitry that detects when the digital power supply is collapsed; the circuitry then presets the analog control signals to the IDDQ state thereby eliminating unwanted leakage current.
Emerging low power standards for USB
For portable devices system designers are looking at ways to reduce power and one area where power can be saved is using low power versions of USB. Two standards are emerging: "Link Power Management" (LPM) and "High Speed Inter-chip USB" (HSIC).
LPM defines a new power sleep state between enable and suspend thereby conserving more power than the present suspend/resume mode. Also sleep mode occurs more often and faster reducing the transitional power states by three orders of magnitude. This reduces power consumption of USB devices and hosts and potentially extending battery life by at least 20 percent of the portable device.
HSIC is USB without the cable or the connector. It allows low power high-speed data transfers (480Mbit/s) using a source synchronous clocked serial interface. Low power is achieved with 1.2V LVCMOS signaling levels that is there no 3.3V signaling.
Summary
Novel circuit techniques can be used to reduce power significantly—enabling integration in very low-power mobile applications. Power reduction techniques include investigating the following:
1. Transmitter architectures 2. Analog signal processing in low-voltage domain 3. Sleep mode power reduction
Technology choice can impact power consumption although an LP technology may not necessarily give the lowest power for high speed serial interconnects. From a systems perspective applications that need to support low power embedded designs and portable devices such as smart phones and mobile internet devices will require new standards such as LPM and HSIC.
References:
"Building High-Quality, Mixed-Signal IP in 65-nm and Beyond" by Chong, Lam, Nandra, Toffolon, IP07, December 2007.
About the author
Navraj Nandra is director of product marketing for the mixed-signal products that include SERDES, USB and DDR2. Navraj holds a masters degree in Microelectronics, majoring in analog IC design, from Brunel University and a post-graduate diploma in Process Technology from Middlesex University.
System designers are influencing the specifications of high speed serial interconnects and a good example of this can be seen with the emerging standards for the USB protocol: LPM and HSIC. USB is prevalent as the high-speed serial interconnect in portable devices such as smart phones and mobile Internet devices. The goal of link power management (LPM) is to reduce power consumption of USB devices and hosts, potentially extending battery life by at least 20 percent. HSIC or "high speed inter-chip USB" allows low power high-speed data transfers (480Mbit/s) using a source synchronous clocked serial interface. Both will be reviewed in this article.
Back to basics: The op amp
In the design of analog/mixed-signal IP many factors contribute to the overall consumption of power. The common methods include:
Simplifying the complexity of the circuit and using folded designs exploiting the complementary properties of NMOS and PMOS devices.
Taking conventional architectures and converting them into designs that consume less power with adaptive biasing.
Gearing the integrated circuit technology towards low power performance by using high Vt processes for example 65nm LP or 40nm LP. Although this may not necessarily reduce power in the active mode as more current is needed to drive the high-speed transmitter in the slower, low power technologies.
Decreasing transistor dimensions together with lowering the supply voltage.
Before delving into power reduction techniques for high speed serial interfaces, consider the case of an operational amplifier as the techniques applied here are pertinent to many other circuit examples.
1. The power consumption of the operational amplifier can be reduced by use of an architecture with only a single (differential) stage. This will reduce the current consumption of the device. However, a method of maximizing the gain, while preserving an acceptable bandwidth and slew rate are now required in the single gain stage.
2. The output stage could be designed to provide sufficient output drive while quiescently consuming as little power as possible.
3. Optimizing the biasing circuit will reduce the power consumption in the op-amp. This is achieved by reducing the internal stage currents by programming an external current in the form of a resistor outside the integrated circuit. Speed, voltage noise and junction leakage will now become major considerations for the designer as these parameters are affected by the value of the bias current programmed.
4. Two important factors that determine the maximum power dissipation in an integrated circuit are the technology used for the design and the type of application. A particular application for CMOS op-amps could be low power switched capacitor filters. If a lower power/low leakage CMOS technology such as 65LP or 40LP is used, then there are two important requirements in the op-amp design. First there must be enough current to charge the compensation capacitor and load capacitor in the required time. Second there must be enough current in the second gain stage transistor to maintain a phase margin of 45 to avoid ringing and degradation of the settling time. If the output current of this circuit is less than the quiescent bias current then this is known as a Class A circuit.
5. Quiescent power dissipation can be reduced by replacing Class A op-amps with Class AB and dynamic op-amps. The Class AB output stage is designed to be biased at small currents so quiescent power dissipation is correspondingly lower.
6. The basic two-stage differential input op-amp can be designed in the sub-threshold current region to minimize the current consumption.
Scaling issues: Is analog anti-Moore?
Whereas scaling of digital circuits is has been investigated in detail, the application of scaling analog circuits is still not that common. For example typical transistor dimensions in an analog circuit are a few multiples larger than 40nm minimum channels.
The sub-threshold characteristics of devices with channel lengths below 2m are very different to devices with larger dimensions. It has been observed that the current becomes exponentially dependent on drain voltage independent of VDS. This effect is sometimes referred to as "drain induced barrier lowering" (DIBL). If this effect can be avoided then IDdecreases exponentially as VGS is reduced below VT.
Scaling devices, and reducing the supply voltage accordingly, will not degrade open circuit voltage gain. Scaling dimensions but keeping supply voltage constant will, however, decrease the gain. The dynamic range of circuits such as op-amps fall because the analog signal range becomes limited due to the reduction in the power supply voltage. The problems of scaling down include fabrication challenges, limitations in the design of devices and circuits and the efficiency and distribution of power supplies.
Thermal noise will remain constant because the device transconductance remains constant under constant field scaling. The 1/f noise intensifies, but the effect of this can be reduced by translating the signal to a higher portion of the frequency spectrum, using chopper stabilization.
Low power guidelines
A set of guidelines can be developed for low power analog design, considering the op-amp as an example: the biasing circuitry, input, output and compensation stages can be examined.
The DC biasing circuitry for the op-amp must provide accurately determined and suitably regulated quiescent biasing currents at very low current levels. The current must be insensitive to changes in temperature, supply voltage and process tolerances.
The configuration of the input stage will dictate whether the op-amp can be used in a single low voltage (1.2V, or lower) supply application. Therefore the following properties are desirable (but not always possible) on a particular low power analog design:
Very low power supply operation using core devices Class B or AB output stage " this reduces the quiescent power dissipation particularly in a leaky process A rail to rail common mode input range A load-capacitance aware compensation scheme Capability to drive a small output load Bandwidth and slew rate commensurate with supply current Getting high precision by keeping offsets low, high input impedance, high CMRR and high PSRR.
Low power design example
The following is an example of a low-power, high-speed driver used in a USB 2.0 PHY. Power is kept very low with the use of a voltage-mode driver, shown in Figure 1.
In fact, for AC-coupled systems such as PCIe, Serial ATA and XAUI, a voltage-mode driver draws 25 percent of the supply current of a current-mode implementation. For example, a classical USB 2.0 driver requires nominal amplitude of 400mV for high-speed data transmission into a 45 load. The static power dissipation from the supply for a current-mode driver is approximately 60mW. Whereas, the power dissipation from the supply for a voltage-mode driver is approximately 30mW.
Another power-reduction technique is to optimize by level shifting down into the low-voltage core device domain as early as possible in the signal path so that device characteristics are leveraged as much as possible in order to reduce power. This strategy enables most high-frequency analog signal processing to be done in the low-voltage domain (for example in the USB, high-speed squelch detection and high speed receive function are implemented using low voltage core devices).
Low-power design is also important in sleep modes (non-functional modes) especially for mobile devices. For example, in the USB protocol the PHY can be held in suspend mode for long periods of time. As a result the power dissipation in this mode can become a significant portion of the total and must be scaled aggressively.
Power gating in digital circuits is often used where more aggressive power reduction is necessary. Power gating helps reduce both channel and gate leakage by collapsing the supply and eliminating the leakage current path. This can be implemented on a sub-block level by implementing collapsible, thick-oxide regulators that can be disabled in low-power modes.
Digital supply leakage often dominates the power down current and so many SoC's collapse the digital (core) supply rail in these modes as well. Doing so can cause serious side effects as analog level-shifters found in MSIP can often cause excessive current draw. Special care in the design of level shifters found in MSIP is necessary to avoid this. One example includes circuitry that detects when the digital power supply is collapsed; the circuitry then presets the analog control signals to the IDDQ state thereby eliminating unwanted leakage current.
Emerging low power standards for USB
For portable devices system designers are looking at ways to reduce power and one area where power can be saved is using low power versions of USB. Two standards are emerging: "Link Power Management" (LPM) and "High Speed Inter-chip USB" (HSIC).
LPM defines a new power sleep state between enable and suspend thereby conserving more power than the present suspend/resume mode. Also sleep mode occurs more often and faster reducing the transitional power states by three orders of magnitude. This reduces power consumption of USB devices and hosts and potentially extending battery life by at least 20 percent of the portable device.
HSIC is USB without the cable or the connector. It allows low power high-speed data transfers (480Mbit/s) using a source synchronous clocked serial interface. Low power is achieved with 1.2V LVCMOS signaling levels that is there no 3.3V signaling.
Summary
Novel circuit techniques can be used to reduce power significantly—enabling integration in very low-power mobile applications. Power reduction techniques include investigating the following:
1. Transmitter architectures 2. Analog signal processing in low-voltage domain 3. Sleep mode power reduction
Technology choice can impact power consumption although an LP technology may not necessarily give the lowest power for high speed serial interconnects. From a systems perspective applications that need to support low power embedded designs and portable devices such as smart phones and mobile internet devices will require new standards such as LPM and HSIC.
References:
"Building High-Quality, Mixed-Signal IP in 65-nm and Beyond" by Chong, Lam, Nandra, Toffolon, IP07, December 2007.
About the author
Navraj Nandra is director of product marketing for the mixed-signal products that include SERDES, USB and DDR2. Navraj holds a masters degree in Microelectronics, majoring in analog IC design, from Brunel University and a post-graduate diploma in Process Technology from Middlesex University.
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