In electronic design and electronic design automation, an intellectual property (IP) block—or IP core—is a unit of reusable design, the use of which has been licensed to a third party. The term is derived from the licensing of the intellectual property rights, such as patents and copyrights, that subsist in the design.
IP cores are for hardware design what libraries are for computer programming. They are typically used much in the style and manner of a discrete integrated circuit on a PCB, where the "circuit board" is a larger ASIC or FPGA design. An IP core commonly takes the form of a computer program written in some HDL—such as Verilog, VHDL, or SystemC—but it can also be a netlist or physical layout, especially in analog electronics.
Altera provides a library of SOPC Builder components (IP cores), which are listed in the table below, for all I/O devices on the DE1 and DE2 boards. You can use these components as part of the SOPC Builder tool in the Quartus® II software. They allow you to easily create Nios® II systems that can access the I/O devices on the DE1 and DE2 boards. Also provided are the associated software drivers that you can incorporate into an Altera® Debug Client project (or an Altera Nios II IDE project). You can install the components in the library using the installer found in the table or download individual IP cores independently. If the IP cores are downloaded independently, you must place them in your project directory or in the sopc_builder\components within the Quartus II install path.
Note: The University Program IP cores are still under development. Several of the cores are available in beta release version. The beta release is supported directly by the Altera Debug Client.
Table 1. University Program IP Cores
IP Cores Description PDF ZIP Development Board Supported
Embedded Processors
Nios II Altera's embedded soft processor
Nios II DE1, DE2
IP Core Bundle
Installer Installs all the available IP cores. The IP cores are listed below. EXE DE1, DE2
Release Notes Description of releases to date TXT
Memory Controller
SRAM Provides read/write access to the SRAM chip PDF ZIP DE1, DE2
SDRAM Provides read/write access to the SDRAM chip and also refreshes the chip automatically PDF ZIP DE1, DE2
FLASH Not available PDF ZIP DE1, DE2
SD Card Not available PDF ZIP DE1, DE2
Communication
RS232 UART Provides a UART over the RS232 port PDF ZIP DE1, DE2
JTAG UART Provides a UART over the JTAG PDF DE1, DE2
Ethernet Not available PDF ZIP DE2
IrDA Provides a UART over the IrDA port PDF ZIP DE2
USB Not available PDF ZIP DE2
Audio/Video
Audio/Video Configuration Automatically configures the audio and video chip PDF ZIP DE1, DE2
Audio In/Out Provides two FIFOs for audio data PDF ZIP DE1, DE2
Video Out Creates timing information for VGA display and has frame buffers for storing picture information PDF ZIP DE1, DE2
Video In Not available PDF ZIP DE2
Input/Output
Parallel Port A generic parallel input/output interface PDF ZIP DE1, DE2
PS/2 Port Serial connection for the PS/2 port PDF ZIP DE1, DE2
16x2 LCD Character Display Connection to the LCD character display PDF ZIP DE2
Avalon® to External Bus Bridge A bus-like interface for a slave device PDF ZIP DE1, DE2
External Bus to Avalon Bridge A bus-like interface for a master device PDF ZIP DE1, DE2
The above IP cores have been developed to support Altera's University Program and its DE1 and DE2 development and education boards. It is important to note that Altera provides a wide range of IP cores to implement industry-standard designs (such as a USB controller or echo cancellation circuitry) and speed system engineering. Altera IP cores are designed to take advantage of the unique features of FPGAs.
Altera offers IP megafunctions for the following technology types:
Embedded Processors (Nios II processors, microcontrollers)
Interfaces and Peripherals (DDR2, PCI, PCI Express)
Digital Signal Processing (fast Fourier transform)
Communications (various physical layers)
View the full listing of available IP cores at the Altera IP MegaStore™.
Commercial IP Core Requests
The Altera University Program provides Altera-developed IP at no charge to qualified research projects at universities. Please contact university@altera.com for more information.
Tuesday, July 29, 2008
Monday, July 21, 2008
Recore Systems New IP
Recore Systems licenses innovative IP for creating advanced digital signal processing platform chips. Recore’s Montium® technology comprises processor cores, design tools for easy integration in customer solutions and ready-to-use applications. Recore offers application implementations for Montium based platforms, IDE tools and hardware IPs.
Recore’s technology enables ultra energy-efficient digital signal processing in products such as cell phones, digital radios/TVs and infotainment and navigation systems. Reuse of Recore’s IP alleviates the avalanching design complexity and costs of today’s chip development. Montium technology allows time multiplexing of different functions on the same hardware and offers a unique combination of flexibility, high performance, low power and low costs.
An excellent engineering team is devoted to create supreme systems-on-chip, with exceptional power and performance characteristics. Recore attracts the best people into all levels of the organization and encourages a stimulating environment, with strong links to leading research centers.
3 Product(s) Listed
Part Number Product Description
Montium DAB/DAB+ Viterbi Decoder Soft IP core implementation of the Viterbi algorithm for Montium tile processors optimized for DAB/DAB+ applications
Montium® FFT/IFFT IP Core FFT/IFFT implementation for Montium Tile Processors
Montium Tile Processor (TP) Dynamically Reconfigurable Digital Signal Processing Tile Processor
Recore’s technology enables ultra energy-efficient digital signal processing in products such as cell phones, digital radios/TVs and infotainment and navigation systems. Reuse of Recore’s IP alleviates the avalanching design complexity and costs of today’s chip development. Montium technology allows time multiplexing of different functions on the same hardware and offers a unique combination of flexibility, high performance, low power and low costs.
An excellent engineering team is devoted to create supreme systems-on-chip, with exceptional power and performance characteristics. Recore attracts the best people into all levels of the organization and encourages a stimulating environment, with strong links to leading research centers.
3 Product(s) Listed
Part Number Product Description
Montium DAB/DAB+ Viterbi Decoder Soft IP core implementation of the Viterbi algorithm for Montium tile processors optimized for DAB/DAB+ applications
Montium® FFT/IFFT IP Core FFT/IFFT implementation for Montium Tile Processors
Montium Tile Processor (TP) Dynamically Reconfigurable Digital Signal Processing Tile Processor
HDL Design House New IP
HDL Design House is a fast growing privately owned company focused on providing synthesizable VHDL/Verilog IP cores, ASIC (SoC) or FPGA design and design verification services.
HDL Design House was incorporated in March of 1999 with the mission to offer world class hardware design services to international customers. The founders have more then 10 years as consulting experts in ASIC/FPGA design for local and international customers. The strong experience and professional background acquired during this period, supplemented by customer satisfaction, encouraged them to found their own company and start to offer hardware design services.
The company has strong background in telecommunications, DSP, computer architecture, high performance computer arithmetic, and different communication protocols. Actively cooperating with USA companies on leading high-tech projects, HDL Design House engineering staff acquired and developed world class expertise in complex ASIC/FPGA design and design management, design verification, and related skills.
HDL Design House has internal IP core development program. Still it can develop IP cores according to the customer specification.
We favor long-term relationship with our customers.
11 Product(s) Listed
Part Number Product Description
HIP 3200 UniPro Soft IP Core
HIP 2900 BCH Codec
HIP 4000 Golay Encoder/Decoder IP Core
HIP 2400 Reed Solomon Encoder IP Core
HIP 2500 Reed Solomon Decoder IP Core
HIP 3000 APB SPI Lite IP Core
HMC FIDWT 39510 Forward and Inverse Discrete Wavelet Transform
HMC FFT 31510 1024-Point Complex FFT/IFFT
HIP 1100 DES/TDES - Full hardware implementation of NIST FIPS PUB 46-3 algorithm (DES/TDES). OCP/AMBA bus interfaces
HIP 1000 AES - Full hardware implementation of NIST FIPS PUB 197 algorithm. 128 bit data and programable 128/192/256 key length
IEEE 1284 IEEE 1284 Parallel Port Controller
HDL Design House was incorporated in March of 1999 with the mission to offer world class hardware design services to international customers. The founders have more then 10 years as consulting experts in ASIC/FPGA design for local and international customers. The strong experience and professional background acquired during this period, supplemented by customer satisfaction, encouraged them to found their own company and start to offer hardware design services.
The company has strong background in telecommunications, DSP, computer architecture, high performance computer arithmetic, and different communication protocols. Actively cooperating with USA companies on leading high-tech projects, HDL Design House engineering staff acquired and developed world class expertise in complex ASIC/FPGA design and design management, design verification, and related skills.
HDL Design House has internal IP core development program. Still it can develop IP cores according to the customer specification.
We favor long-term relationship with our customers.
11 Product(s) Listed
Part Number Product Description
HIP 3200 UniPro Soft IP Core
HIP 2900 BCH Codec
HIP 4000 Golay Encoder/Decoder IP Core
HIP 2400 Reed Solomon Encoder IP Core
HIP 2500 Reed Solomon Decoder IP Core
HIP 3000 APB SPI Lite IP Core
HMC FIDWT 39510 Forward and Inverse Discrete Wavelet Transform
HMC FFT 31510 1024-Point Complex FFT/IFFT
HIP 1100 DES/TDES - Full hardware implementation of NIST FIPS PUB 46-3 algorithm (DES/TDES). OCP/AMBA bus interfaces
HIP 1000 AES - Full hardware implementation of NIST FIPS PUB 197 algorithm. 128 bit data and programable 128/192/256 key length
IEEE 1284 IEEE 1284 Parallel Port Controller
Denali Announces New LPDDR2 Memory Controller and PHY Solution
First Provider of Memory Controller and PHY Solution to Support LPDDR2 in Next-Generation Mobile and Embedded Applications
SUNNYVALE, Calif. -- July 21, 2008 -- Denali, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its Databahn(TM) memory controller and PHY IP supports the pre-released LPDDR2 specification, as currently defined by JEDEC -- the leading developer of standards for the solid-state industry. Chip designers and system architects desiring to upgrade to LPDDR2 can learn more about Denali's new upcoming LPDDR2 offering, which will include both varieties of SDRAM (S2/S4) in the memory controller and PHY IP and support for Non-Volatile Memory (NVM) by attending the MemCon presentation, "Next-Generation Low-Power LPDDR2 Memories: How to Use Them in Your Mobile and Embedded Designs" at 1:30pm on Wednesday, July 23 in Santa Clara, CA. Denali's Databahn LPDDR2 memory controller and PHY will be well suited for low power and embedded system designs which target applications as cell phones, ultra-mobile PCs, and consumer applications, addressing design requirements of density, speed, and power.
"We are pleased to see member companies introduce next-generation technologies that fully support the LPDDR2 industry specification. It is this type of advanced industry adoption that helps to establish high quality and reliability benchmarks required for low power and embedded system memory design," said Roger Isaac, chair for the JEDEC JC-42.6 Low Power Memory Committee. "Denali is an active committee participant, working closely with memory vendors like Spansion to provide valuable recommendations toward the development of the specification."
Denali's LPDDR2 memory controller and PHY will support the full specification when released by JEDEC. LPDDR2 addresses the needs of mobile and consumer systems where the "PC memory" devices, DDR2 and DDR3, are unsuitable, as LPDDR2 offers a low power, low voltage, low pin-count memory in a range of densities and speeds that are closely matched to the needs of those mobile and consumer systems. In addition, LPDDR2 was designed to allow sharing of SDRAM and NVM memory on the same bus, which is extremely difficult in PC memory technologies. For immediate availability of a C-model, in advance of the silicon IP for Denali's Databahn LPDDR2 memory controller and PHY, contact sales@denali.com.
"Many of our customers are looking for ways to upgrade to new controller technologies and are faced with several challenges," states Marc Greenberg, director of Technical Marketing for Databahn products at Denali Software. "Many of the LPDDR2 features are derived from the best features of the LPDDR1, DDR2 and DDR3 technologies that we already support. This gives Denali an accelerated position to support the LPDDR2 architecture and continue to provide our customers with high-quality, interoperable, and configurable IP solutions."
About Databahn Solutions
Denali's Databahn DDR DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, and LP-DDR devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification test bench, static timing analysis (STA) scripts, programmable register settings, documentation, I/O pads and packaging. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://www.denali.com/dram.
About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.
SUNNYVALE, Calif. -- July 21, 2008 -- Denali, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its Databahn(TM) memory controller and PHY IP supports the pre-released LPDDR2 specification, as currently defined by JEDEC -- the leading developer of standards for the solid-state industry. Chip designers and system architects desiring to upgrade to LPDDR2 can learn more about Denali's new upcoming LPDDR2 offering, which will include both varieties of SDRAM (S2/S4) in the memory controller and PHY IP and support for Non-Volatile Memory (NVM) by attending the MemCon presentation, "Next-Generation Low-Power LPDDR2 Memories: How to Use Them in Your Mobile and Embedded Designs" at 1:30pm on Wednesday, July 23 in Santa Clara, CA. Denali's Databahn LPDDR2 memory controller and PHY will be well suited for low power and embedded system designs which target applications as cell phones, ultra-mobile PCs, and consumer applications, addressing design requirements of density, speed, and power.
"We are pleased to see member companies introduce next-generation technologies that fully support the LPDDR2 industry specification. It is this type of advanced industry adoption that helps to establish high quality and reliability benchmarks required for low power and embedded system memory design," said Roger Isaac, chair for the JEDEC JC-42.6 Low Power Memory Committee. "Denali is an active committee participant, working closely with memory vendors like Spansion to provide valuable recommendations toward the development of the specification."
Denali's LPDDR2 memory controller and PHY will support the full specification when released by JEDEC. LPDDR2 addresses the needs of mobile and consumer systems where the "PC memory" devices, DDR2 and DDR3, are unsuitable, as LPDDR2 offers a low power, low voltage, low pin-count memory in a range of densities and speeds that are closely matched to the needs of those mobile and consumer systems. In addition, LPDDR2 was designed to allow sharing of SDRAM and NVM memory on the same bus, which is extremely difficult in PC memory technologies. For immediate availability of a C-model, in advance of the silicon IP for Denali's Databahn LPDDR2 memory controller and PHY, contact sales@denali.com.
"Many of our customers are looking for ways to upgrade to new controller technologies and are faced with several challenges," states Marc Greenberg, director of Technical Marketing for Databahn products at Denali Software. "Many of the LPDDR2 features are derived from the best features of the LPDDR1, DDR2 and DDR3 technologies that we already support. This gives Denali an accelerated position to support the LPDDR2 architecture and continue to provide our customers with high-quality, interoperable, and configurable IP solutions."
About Databahn Solutions
Denali's Databahn DDR DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, and LP-DDR devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification test bench, static timing analysis (STA) scripts, programmable register settings, documentation, I/O pads and packaging. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://www.denali.com/dram.
About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.
Thursday, July 17, 2008
Gaisler Research AB Silicon IP Cores
Gaisler Research AB is a provider of SoC solutions for exceptionally competitive markets such as Aerospace, Military and demanding Commercial applications. The Gaisler Research's products consist of user-customizable 32-bit SPARC V8 processor cores, peripheral IP-cores and associated software and development tools. Gaisler Research solutions help companies develop highly competitive customer and application-specific SoC designs.
20 Product(s) Listed
Part Number Product Description
GRLIB Configurable AMBA bus SoC platform
LOGAN On-Chip Logic Analyzer
GRUSBHC USB 2.0 Host Controller
AHB2AHB Uni-directional AMBA AHB to AHB bridge
AHBBRIDGE Bi-directional AMBA AHB/AHB bridge
GRCAN CAN 2.0 Controller with DMA
RS_GF4 Reed-Solomon Memory Protection Codec
SSRCRTL 32-bit SSRAM/PROM Controller
SRCTRL 32-bit SRAM/PROM Controller
SDCRTL 32/64-bit PC133 SDRAM Controller
DDRSPA Single-port 16/32/64-bit DDR266 Controller
GRPCI 32-bit PCI Bus Master/Target
LEON3 32-bit SPARC V8 processor
GRETH_GBIT 10/100/1000 MBit Ethernet MAC
GRECC Elliptic Curve Cryptography (ECC) core with AMBA APB interface
GRAES Advanced Encryption Standard (AES-128) core with AMBA AHB interface
GRETH 10/100 Mbit Ethernet MAC
GRSPW Spacewire Codec with AHB host interface
GR1553 AMBA interface for Actel MIL-STD-1553B Cores
GRFPU-1 Single- and double-precision IEEE-754 floating-point unit
20 Product(s) Listed
Part Number Product Description
GRLIB Configurable AMBA bus SoC platform
LOGAN On-Chip Logic Analyzer
GRUSBHC USB 2.0 Host Controller
AHB2AHB Uni-directional AMBA AHB to AHB bridge
AHBBRIDGE Bi-directional AMBA AHB/AHB bridge
GRCAN CAN 2.0 Controller with DMA
RS_GF4 Reed-Solomon Memory Protection Codec
SSRCRTL 32-bit SSRAM/PROM Controller
SRCTRL 32-bit SRAM/PROM Controller
SDCRTL 32/64-bit PC133 SDRAM Controller
DDRSPA Single-port 16/32/64-bit DDR266 Controller
GRPCI 32-bit PCI Bus Master/Target
LEON3 32-bit SPARC V8 processor
GRETH_GBIT 10/100/1000 MBit Ethernet MAC
GRECC Elliptic Curve Cryptography (ECC) core with AMBA APB interface
GRAES Advanced Encryption Standard (AES-128) core with AMBA AHB interface
GRETH 10/100 Mbit Ethernet MAC
GRSPW Spacewire Codec with AHB host interface
GR1553 AMBA interface for Actel MIL-STD-1553B Cores
GRFPU-1 Single- and double-precision IEEE-754 floating-point unit
Aeroflex Incorporated Announces the Purchase of Gaisler Research AB
Aeroflex Incorporated today announced the acquisition of Gaisler Research AB, a privately held company, located in Gothenburg, Sweden.
Gaisler is a world leader in the development and support of IP cores and development tools for commercial and aerospace embedded processors based on the SPARC architecture. Gaisler’s flagship product is the LEON synthesizable processor which includes a full development environment and a library of IP support cores (GRLIB). The LEON processor architecture is an established solution for commercial and aerospace markets providing the designer with a flexible design environment for customization to individual requirements. Established in 2001, the Gaisler core design team is positioned as the pre-eminent processor design team for European markets with complete in-house design facilities for microprocessor, ASIC and field programmable gate array-based designs. With over 40 years of combined staff design experience, Gaisler has been involved in establishing past and current European standards for processor and ASIC development.
John Buyko, President, Aeroflex Microelectronic Solutions said, “Aeroflex is pleased that Gaisler Research is joining our team. This strategic acquisition provides Aeroflex with immediate improvement and synergy in our IP, software, and microprocessor design expertise, product solutions and technology roadmaps. The Gaisler portfolio will provide significant complimentary enhancements to our existing portfolio and further solidifies Aeroflex’s position as a leading supplier to our customers.”
About Aeroflex
Aeroflex Incorporated is a global provider of high technology solutions to the aerospace, defense and broadband communications markets. The Company’s diverse technologies allow it to design, develop, manufacture and market a broad range of test, measurement and microelectronic products. Additional information concerning Aeroflex Incorporated can be found on the Company’s website: www.aeroflex.com.
Gaisler is a world leader in the development and support of IP cores and development tools for commercial and aerospace embedded processors based on the SPARC architecture. Gaisler’s flagship product is the LEON synthesizable processor which includes a full development environment and a library of IP support cores (GRLIB). The LEON processor architecture is an established solution for commercial and aerospace markets providing the designer with a flexible design environment for customization to individual requirements. Established in 2001, the Gaisler core design team is positioned as the pre-eminent processor design team for European markets with complete in-house design facilities for microprocessor, ASIC and field programmable gate array-based designs. With over 40 years of combined staff design experience, Gaisler has been involved in establishing past and current European standards for processor and ASIC development.
John Buyko, President, Aeroflex Microelectronic Solutions said, “Aeroflex is pleased that Gaisler Research is joining our team. This strategic acquisition provides Aeroflex with immediate improvement and synergy in our IP, software, and microprocessor design expertise, product solutions and technology roadmaps. The Gaisler portfolio will provide significant complimentary enhancements to our existing portfolio and further solidifies Aeroflex’s position as a leading supplier to our customers.”
About Aeroflex
Aeroflex Incorporated is a global provider of high technology solutions to the aerospace, defense and broadband communications markets. The Company’s diverse technologies allow it to design, develop, manufacture and market a broad range of test, measurement and microelectronic products. Additional information concerning Aeroflex Incorporated can be found on the Company’s website: www.aeroflex.com.
Tensilica Appoints Semiconductor Industry Veteran Jack Guedj as New President and CEO
Founder Chris Rowen Becomes CTO to Drive Advanced Processor Technology
SANTA CLARA, Calif. – July 16, 2008 - Expanding its executive team with the talented leadership required to take the company into its next phase of growth, Tensilica, Inc. today announced it has appointed Dr. Jack Guedj, Ph.D. as the company’s president and chief executive officer (CEO). Guedj has extensive experience as a senior executive with a variety of fast-growing start-ups and high-profile semiconductor companies focused in high-performance communications and multimedia. He succeeds Dr. Chris Rowen, founder of Tensilica, who is now the company’s chief technology officer (CTO), driving advanced processor technology and applications in close partnership with Tensilica’s strategic customers. Rowen will continue to serve on the Tensilica board of directors.
“Tensilica’s customizable and standard processors are used broadly by a growing portfolio of customers who realize the benefits of flexible, optimized processor cores,” said Chris Rowen. “As our products continue to be adopted by an increasing customer base, the company is experiencing significant financial and operational growth, requiring the strengthening of our leadership team. Jack’s proven track record as a successful, savvy business leader makes him the ideal candidate to lead Tensilica at this exciting time.”
Rowen’s transition to the CTO position will enable him to fully focus on driving the long-term evolution of the customizable processor technology and its use by strategic customers. As founder of Tensilica in 1997 and inventor of its groundbreaking Xtensa processor technology and design methodology, he will continue to be an integral part of the company’s growth strategy. Under his guidance, Tensilica has secured over 130 licensees with a run rate of over 200 million processor cores shipped per year.
“I believe there is opportunity for substantial growth in Tensilica’s customizable processors and complete standard IP cores, in particular, in the consumer multimedia, wireless and wired communications, and computing application segments,” said Guedj. “Tensilica’s patented, automated processor design tools help designers quickly craft the best price/performance processors, lowering risk and providing the ability to evolve the hardware via programmability..”
Most recently, Guedj was president and CEO of Magnum Semiconductor, a leading provider of chips, software, and platforms for consumer entertainment and professional broadcast. Guedj spun Magnum out of Cirrus Logic in 2005. Under his leadership, he successfully led Magnum’s growth from its founding stage through the acquisition of LSI Logic’s consumer product group. Prior to Cirrus Logic, he was president of TVIA, a leading provider of digital display processors, and he led the company’s initial public offering in 2000. He is also a former vice president of sales and marketing at video set-top box and chip supplier, Faroudja, and director of digital media/residential broadband segments at National Semiconductor. He holds master’s and doctorate degrees in electronics from the University of Paris, as well as a master’s degree in business from UCLA.
“Jack’s proven track record gives him the experience Tensilica needs as it comes of age as a major supplier of optimized processor cores,” stated Harvey Jones, Tensilica’s chairman of the board. “The combination of these two highly talented top executives really strengthens the management team for the growth the company is already experiencing.”
About Tensilica
Tensilica, Inc., is the recognized leader in customizable and standard processors and DSPs for flexible audio, video, imaging, security, networking, and baseband signal processing. The modern design behind all of Tensilica’s processor cores powers top tier semiconductor companies, innovative start-ups, and system OEMs for high-volume products including mobile phones and other wireless devices, computer peripherals, storage devices, networking and communications equipment, and consumer electronics devices including portable media players, digital TV, and broadband set top boxes. For more information on Tensilica’s patented, benchmark-proven processors, visit www.tensilica.com.
SANTA CLARA, Calif. – July 16, 2008 - Expanding its executive team with the talented leadership required to take the company into its next phase of growth, Tensilica, Inc. today announced it has appointed Dr. Jack Guedj, Ph.D. as the company’s president and chief executive officer (CEO). Guedj has extensive experience as a senior executive with a variety of fast-growing start-ups and high-profile semiconductor companies focused in high-performance communications and multimedia. He succeeds Dr. Chris Rowen, founder of Tensilica, who is now the company’s chief technology officer (CTO), driving advanced processor technology and applications in close partnership with Tensilica’s strategic customers. Rowen will continue to serve on the Tensilica board of directors.
“Tensilica’s customizable and standard processors are used broadly by a growing portfolio of customers who realize the benefits of flexible, optimized processor cores,” said Chris Rowen. “As our products continue to be adopted by an increasing customer base, the company is experiencing significant financial and operational growth, requiring the strengthening of our leadership team. Jack’s proven track record as a successful, savvy business leader makes him the ideal candidate to lead Tensilica at this exciting time.”
Rowen’s transition to the CTO position will enable him to fully focus on driving the long-term evolution of the customizable processor technology and its use by strategic customers. As founder of Tensilica in 1997 and inventor of its groundbreaking Xtensa processor technology and design methodology, he will continue to be an integral part of the company’s growth strategy. Under his guidance, Tensilica has secured over 130 licensees with a run rate of over 200 million processor cores shipped per year.
“I believe there is opportunity for substantial growth in Tensilica’s customizable processors and complete standard IP cores, in particular, in the consumer multimedia, wireless and wired communications, and computing application segments,” said Guedj. “Tensilica’s patented, automated processor design tools help designers quickly craft the best price/performance processors, lowering risk and providing the ability to evolve the hardware via programmability..”
Most recently, Guedj was president and CEO of Magnum Semiconductor, a leading provider of chips, software, and platforms for consumer entertainment and professional broadcast. Guedj spun Magnum out of Cirrus Logic in 2005. Under his leadership, he successfully led Magnum’s growth from its founding stage through the acquisition of LSI Logic’s consumer product group. Prior to Cirrus Logic, he was president of TVIA, a leading provider of digital display processors, and he led the company’s initial public offering in 2000. He is also a former vice president of sales and marketing at video set-top box and chip supplier, Faroudja, and director of digital media/residential broadband segments at National Semiconductor. He holds master’s and doctorate degrees in electronics from the University of Paris, as well as a master’s degree in business from UCLA.
“Jack’s proven track record gives him the experience Tensilica needs as it comes of age as a major supplier of optimized processor cores,” stated Harvey Jones, Tensilica’s chairman of the board. “The combination of these two highly talented top executives really strengthens the management team for the growth the company is already experiencing.”
About Tensilica
Tensilica, Inc., is the recognized leader in customizable and standard processors and DSPs for flexible audio, video, imaging, security, networking, and baseband signal processing. The modern design behind all of Tensilica’s processor cores powers top tier semiconductor companies, innovative start-ups, and system OEMs for high-volume products including mobile phones and other wireless devices, computer peripherals, storage devices, networking and communications equipment, and consumer electronics devices including portable media players, digital TV, and broadband set top boxes. For more information on Tensilica’s patented, benchmark-proven processors, visit www.tensilica.com.
Tuesday, July 15, 2008
Intel And Micron First To Deliver Sub-40 Nanometer NAND Flash Memory Device
New 34 Nanometer 32 Gigabit NAND Chip is Industry’s Most Advanced NAND Process Technology Available Enabling Increased Storage Capacity in Small Form-Factor Applications
Boise, Idaho and Santa Clara, Calif. , Thursday, May 29, 2008 – Today Intel Corporation and Micron Technology, Inc. introduced the industry’s first sub-40 nanometer (nm) NAND memory device, unveiling a 34nm 32 gigabit (Gb) multi-level cell chip. This process technology was jointly developed by Intel and Micron and manufactured by the companies’ NAND flash joint venture, IM Flash Technologies (IMFT). It is the smallest NAND process geometry on the market. The 32 Gb NAND chip is the only monolithic device at this density that fits into a standard 48-lead thin small-outline package (TSOP), providing a cost-effective path to higher densities in existing applications. Shipments of customer samples begin in June and mass production is expected during the second half of this calendar year.
“This new 32 Gb device provides the best bit storage density available in the industry,” said Brian Shirley, vice president of Micron’s Memory Group. “Together with our partners at Intel, we’re proud to have now taken the lead in production process technology.”
“The introduction of 34nm process technology highlights IMFT’s rapid progress and moves us to the forefront of NAND process technology,” said Pete Hazen, director of marketing, Intel NAND Products Group. “These advancements will expand the value proposition and accelerate the adoption of solid-state drive (SSD) solutions in computing platforms.”
The 34nm 32 Gb chips will be manufactured on 300 millimeter wafers, each producing approximately 1.6 terabytes of NAND. Measuring just 172mm², less than the size of a thumbnail, the 34nm 32 Gb chip will cost-effectively enable high-density solid-state storage in small form factor applications.
A single 32 Gb chip could store more than 2,000 high-resolution digital photos or hold up to 1,000 songs on a personal music player.
Two 8-die stacked packages would realize 64 gigabytes (GBs) of storage, enough for recording anywhere from eight to 40 hours of high-definition video in a digital camcorder.
The 34nm 32Gb chip was designed with solid-state drives in mind. The product will enable more cost-effective SSDs, instantly doubling the current storage volume of these devices and driving capacities to beyond 256 GBs in today’s standard, smaller 1.8-inch form factor. SSDs are becoming the new storage medium for notebook computers, providing lower power, faster boot-up time, increased reliability, improved performance and reduced noise than hard disk drives. With the innovations in NAND process technology, such as with the 34nm NAND process, SSDs now offer a significant range of capacities to meet market requirements.
Based on the 34nm architecture, Intel and Micron also plan to introduce lower density multi-level cell products including single-level cell products, by the end of this calendar year.
About Intel
Intel (NASDAQ: INTC), the world leader in silicon innovation, develops technologies, products and initiatives to continually advance how people work and live. Additional information about Intel is available at www.intel.com/pressroom and http://blogs.intel.com. For more details on Intel NAND flash products go to www.intel.com/design/flash/nand.
About Micron
Micron Technology, Inc., is one of the world's leading providers of advanced semiconductor solutions. Through its worldwide operations, Micron manufactures and markets DRAMs, NAND flash memory, CMOS image sensors, other semiconductor components, and memory modules for use in leading-edge computing, consumer, networking, and mobile products. Micron’s common stock is traded on the New York Stock Exchange (NYSE) under the MU symbol. To learn more about Micron Technology, Inc., visit www.micron.com.
©2008 Micron Technology, Inc., and Intel Corporation. All rights reserved. Information is subject to change without notice.
Micron and the Micron logo are trademarks of Micron Technology, Inc. Intel is a trademark of Intel Corporation in the United States and other countries. All other trademarks are the property of their respective owners.
This press release contains forward-looking statements regarding the production of the 34nm 32 Gb NAND device. Actual events or results may differ materially from those contained in the forward-looking statements. Please refer to the documents the Company files on a consolidated basis from time to time with the Securities and Exchange Commission, specifically the Company's most recent Form 10-K and Form 10-Q. These documents contain and identify important factors that could cause the actual results for the Company on a consolidated basis to differ materially from those contained in our forward-looking statements (see Certain Factors). Although we believe that the expectations reflected in the forward-looking statements are reasonable, we cannot guarantee future results, levels of activity, performance or achievements.
Boise, Idaho and Santa Clara, Calif. , Thursday, May 29, 2008 – Today Intel Corporation and Micron Technology, Inc. introduced the industry’s first sub-40 nanometer (nm) NAND memory device, unveiling a 34nm 32 gigabit (Gb) multi-level cell chip. This process technology was jointly developed by Intel and Micron and manufactured by the companies’ NAND flash joint venture, IM Flash Technologies (IMFT). It is the smallest NAND process geometry on the market. The 32 Gb NAND chip is the only monolithic device at this density that fits into a standard 48-lead thin small-outline package (TSOP), providing a cost-effective path to higher densities in existing applications. Shipments of customer samples begin in June and mass production is expected during the second half of this calendar year.
“This new 32 Gb device provides the best bit storage density available in the industry,” said Brian Shirley, vice president of Micron’s Memory Group. “Together with our partners at Intel, we’re proud to have now taken the lead in production process technology.”
“The introduction of 34nm process technology highlights IMFT’s rapid progress and moves us to the forefront of NAND process technology,” said Pete Hazen, director of marketing, Intel NAND Products Group. “These advancements will expand the value proposition and accelerate the adoption of solid-state drive (SSD) solutions in computing platforms.”
The 34nm 32 Gb chips will be manufactured on 300 millimeter wafers, each producing approximately 1.6 terabytes of NAND. Measuring just 172mm², less than the size of a thumbnail, the 34nm 32 Gb chip will cost-effectively enable high-density solid-state storage in small form factor applications.
A single 32 Gb chip could store more than 2,000 high-resolution digital photos or hold up to 1,000 songs on a personal music player.
Two 8-die stacked packages would realize 64 gigabytes (GBs) of storage, enough for recording anywhere from eight to 40 hours of high-definition video in a digital camcorder.
The 34nm 32Gb chip was designed with solid-state drives in mind. The product will enable more cost-effective SSDs, instantly doubling the current storage volume of these devices and driving capacities to beyond 256 GBs in today’s standard, smaller 1.8-inch form factor. SSDs are becoming the new storage medium for notebook computers, providing lower power, faster boot-up time, increased reliability, improved performance and reduced noise than hard disk drives. With the innovations in NAND process technology, such as with the 34nm NAND process, SSDs now offer a significant range of capacities to meet market requirements.
Based on the 34nm architecture, Intel and Micron also plan to introduce lower density multi-level cell products including single-level cell products, by the end of this calendar year.
About Intel
Intel (NASDAQ: INTC), the world leader in silicon innovation, develops technologies, products and initiatives to continually advance how people work and live. Additional information about Intel is available at www.intel.com/pressroom and http://blogs.intel.com. For more details on Intel NAND flash products go to www.intel.com/design/flash/nand.
About Micron
Micron Technology, Inc., is one of the world's leading providers of advanced semiconductor solutions. Through its worldwide operations, Micron manufactures and markets DRAMs, NAND flash memory, CMOS image sensors, other semiconductor components, and memory modules for use in leading-edge computing, consumer, networking, and mobile products. Micron’s common stock is traded on the New York Stock Exchange (NYSE) under the MU symbol. To learn more about Micron Technology, Inc., visit www.micron.com.
©2008 Micron Technology, Inc., and Intel Corporation. All rights reserved. Information is subject to change without notice.
Micron and the Micron logo are trademarks of Micron Technology, Inc. Intel is a trademark of Intel Corporation in the United States and other countries. All other trademarks are the property of their respective owners.
This press release contains forward-looking statements regarding the production of the 34nm 32 Gb NAND device. Actual events or results may differ materially from those contained in the forward-looking statements. Please refer to the documents the Company files on a consolidated basis from time to time with the Securities and Exchange Commission, specifically the Company's most recent Form 10-K and Form 10-Q. These documents contain and identify important factors that could cause the actual results for the Company on a consolidated basis to differ materially from those contained in our forward-looking statements (see Certain Factors). Although we believe that the expectations reflected in the forward-looking statements are reasonable, we cannot guarantee future results, levels of activity, performance or achievements.
AMD slashes $880M from value of division
SAN JOSE, Calif. - Struggling to climb back to profitability, Advanced Micro Devices Inc. suffered another setback Friday when the chip maker disclosed that two businesses it acquired in a pricey acquisition were underperforming.
AMD said the businesses' values would have to be reduced by $880 million. It's the second time AMD has had to slash the value of businesses it absorbed as part of its pricey — and controversial — acquisition of graphics chip maker ATI Technologies Inc.
Shares in AMD fell 12 cents, or 2.4 percent, to $4.84 Friday, after earlier changing hands at $4.60, their lowest point since October 2002.
Sunnyvale-based AMD is the world's No. 2 maker of microprocessors, the brains of personal computers.
AMD and its much-larger rival, Intel Corp., are both pushing deeper into graphics technologies, typically handled on separate chips, as the demand intensifies on computers to render better graphics for Internet video, computer games and high-definition movies.
Santa Clara-based Intel has chosen to beef up the graphics capabilities of its chips in-house, while AMD decided to buy its way in with the $5.6 billion acquisition of ATI in October 2006, a decision that is still hurting the company financially.
AMD is now the world's second-largest maker of standalone graphics chips, behind Santa Clara-based Nvidia Corp.
In a filing with the Securities and Exchange Commission, AMD said it recently discovered that its business units that make chips for cell phones and digital televisions, both acquired as part of the ATI transaction and considered "noncore" parts of AMD's operations, weren't performing up to expectations.
As a result, the company plans to write down the value of their goodwill, or intangible assets such as reputation, and take charges of $880 million in the latest quarter, which ended June 28.
AMD had previously written down ATI's overall value by $1.6 billion in January, in a staggering reassessment that indicated the perception of ATI in the market had slipped dramatically.
Taken together, AMD has effectively said that ATI is now worth 44 percent less as a company than when AMD bought it.
Investors have punished AMD's stock as they await word about the company's plans to sell off slumping business units or even some of its factories, a huge expense for semiconductor companies. More details could emerge Thursday when AMD reports financial results for the second quarter.
AMD was flying high just two years ago, with a stock near $40 a share in February 2006, as AMD was stealing substantial market share from Intel in the lucrative server business, a market AMD didn't enter until 2003. But its fortunes have faded since then on investors' concerns about the company's huge losses and faltering competitive position.
AMD has racked up more than $4 billion in losses over the last year and a half as competition from Intel intensifies and AMD struggles to recover from its own product delays.
AMD also said Friday that it plans to take a $32 million restructuring charge in the latest quarter, mostly for employee severance payments. The company plans to cut 10 percent of its global work force, or about 1,600 workers, by September.
AMD is also writing down $36 million in the value of its short-term investments in the latest quarter, stemming from its stake in Spansion Inc., which makes flash memory chips, and holdings in auction rate securities.
Meanwhile, the company expects to record a gain of $190 million from the sale of some chip-making equipment.
AMD said the businesses' values would have to be reduced by $880 million. It's the second time AMD has had to slash the value of businesses it absorbed as part of its pricey — and controversial — acquisition of graphics chip maker ATI Technologies Inc.
Shares in AMD fell 12 cents, or 2.4 percent, to $4.84 Friday, after earlier changing hands at $4.60, their lowest point since October 2002.
Sunnyvale-based AMD is the world's No. 2 maker of microprocessors, the brains of personal computers.
AMD and its much-larger rival, Intel Corp., are both pushing deeper into graphics technologies, typically handled on separate chips, as the demand intensifies on computers to render better graphics for Internet video, computer games and high-definition movies.
Santa Clara-based Intel has chosen to beef up the graphics capabilities of its chips in-house, while AMD decided to buy its way in with the $5.6 billion acquisition of ATI in October 2006, a decision that is still hurting the company financially.
AMD is now the world's second-largest maker of standalone graphics chips, behind Santa Clara-based Nvidia Corp.
In a filing with the Securities and Exchange Commission, AMD said it recently discovered that its business units that make chips for cell phones and digital televisions, both acquired as part of the ATI transaction and considered "noncore" parts of AMD's operations, weren't performing up to expectations.
As a result, the company plans to write down the value of their goodwill, or intangible assets such as reputation, and take charges of $880 million in the latest quarter, which ended June 28.
AMD had previously written down ATI's overall value by $1.6 billion in January, in a staggering reassessment that indicated the perception of ATI in the market had slipped dramatically.
Taken together, AMD has effectively said that ATI is now worth 44 percent less as a company than when AMD bought it.
Investors have punished AMD's stock as they await word about the company's plans to sell off slumping business units or even some of its factories, a huge expense for semiconductor companies. More details could emerge Thursday when AMD reports financial results for the second quarter.
AMD was flying high just two years ago, with a stock near $40 a share in February 2006, as AMD was stealing substantial market share from Intel in the lucrative server business, a market AMD didn't enter until 2003. But its fortunes have faded since then on investors' concerns about the company's huge losses and faltering competitive position.
AMD has racked up more than $4 billion in losses over the last year and a half as competition from Intel intensifies and AMD struggles to recover from its own product delays.
AMD also said Friday that it plans to take a $32 million restructuring charge in the latest quarter, mostly for employee severance payments. The company plans to cut 10 percent of its global work force, or about 1,600 workers, by September.
AMD is also writing down $36 million in the value of its short-term investments in the latest quarter, stemming from its stake in Spansion Inc., which makes flash memory chips, and holdings in auction rate securities.
Meanwhile, the company expects to record a gain of $190 million from the sale of some chip-making equipment.
Samsung rumors pour cold water on Semicon
SAN FRANCISCO — Rumors that Samsung Electronics Co. Ltd. this week pushed out its fab-tool orders sent shock waves at the Semicon West trade show here, putting vendors in a somber and gloomy mood. The chain of events also prompted many to predict an acceleration of the current shakeout taking place in the fab-tool arena.
The semiconductor-equipment market was already in the midst of a slowdown amid what some call a ''disconnect'' in the sector. Fab utilization rates remain high, but capital spending is down by some 20-to-25 percent due to a lull in ICs.
Compounding the ''disconnect'' at Semicon West is a solar event, which is running in tandem at the show. While there is a buzz at the Intersolar event, the semiconductor fab-tool portion of the show is relatively quiet, with vendors grumbling about the lack of foot traffic in their booths.
Reports that Samsung is now putting the brakes on its capital spending exacerbated the doom-and-gloom sentiment. Samsung is the world's largest buyer of capital equipment, surpassing Intel Corp. several years ago, it was noted.
Amid the Samsung rumors, many are beginning to whisper the ''D'' word: downturn. Still others say it's much worse and calling it a depression.
The net effect: Expect an acceleration of the ongoing shakeout in the fab-tool and electronics materials industries. The strong will get stronger and the weak will not survive over the long haul.
Which companies are the next takeover targets? Axcelis, ASMI and Asyst are currently fending off unfriendly takeover bids. Perhaps some big-name players--Lam, Novellus and Varian--are in play. Most certainty, the new startups will be the first takeover targets.
Clearly, the landscape will change--again. Indeed, the current outlook reminds many of the severe and deep downturn in 2001. The semiconductor-equipment market is projected to hit $34.12 billion in 2008, down 20 percent over 2007, according to SEMI.
In comparison, the fab-tool market grew by 6 percent in 2007, according to SEMI (San Jose, Calif.). Following the downturn in 2008, the semiconductor-equipment market is projected to rebound with annual growth of 13 percent and 6 percent in 2009 and 2010, respectively, according to the trade group.
The poor climate in 2008 is due to ''lower spending in the memory sector and a less than favorable device pricing environment,'' said Stanley Myers, president and CEO, of SEMI at a press event.
Capital spending in the memory sector is especially troublesome, said Rick Hill, president and chief executive of Novellus Systems Inc. (San Jose, Calif.) "No one can argue that memory is under pressure,'' Hill said during the company's analyst meeting. "Do I think the market will get better when I wake up in the morning? Hell no. I need Maalox every morning.''
In addition to the business woes, the U.S. sub-prime mortgage crisis and soaring oil prices ''creates uncertainties'' in the overall economy, thereby impacting consumer spending for electronic goods, said Harvey Frye, president of Tokyo Electron America Inc. (Austin, Texas). Tokyo Electron America is the U.S. subsidiary of Japanese semiconductor equipment giant Tokyo Electron Ltd. (TEL).
A poor memory environment, coupled with economic woes, spells bad news for vendors. ''This is a big downturn," declared Mike Splinter, president and CEO of Applied Materials Inc. (Santa Clara, Calif.), at the company's analyst meeting.
Overall, semiconductor equipment is a ''tough market," he said. Originally, Applied projected that the front-end equipment market would fall by 5-to-15 percent in 2008 over 2007. Now, the world's largest equipment vendor projects that the wafer-fab equipment segment could fall bt 25-to-30 percent this year, he said.
On the bright side, flat-panel displays are still growing and capital spending could jump by 30 percent in 208. "Capex has been bigger than what we expected,'' he said.
Applied, which has made a number of acquisitions in the solar-gear market, also sees strong growth in that business. The company ''has not caught up'' with demand for solar gear, he added.
2009 forecast
Going forward, some see a slight recovery in 2009. Others see a prolonged downturn.
Much of the recovery hinges on the memory market. But a recovery ''is hard to predict,'' said Brian Trafas, chief marketing officer at KLA-Tencor Corp. (San Jose, Calif.). "Until we see an uptick in memory pricing, it's hard to see any capacity buys.''
"2009 looks like a flattish year," said Jerry Cutini, president and CEO of Aviza Technology Inc. (Scotts Valley, Calif.) ''Flat would be considered good in 2009.''
2009 could take a turn for the worse--if, say, oil prices continue to soar. "If oil goes to $200 a barrel, it's going to be a bad year,'' he said.
During a presentation, Tom St. Dennis, senior vice president and general manager of the Silicon Systems Group at Applied Materials, listed several drivers that could bring the industry out of its slump. Among the major drivers are DDR3 memory, solid-state storage drives, and next-generation communications and graphics chips, he said.
What is clear that the landscape will change in semiconductor equipment. For example, no less than three vendors are fighting off hostile takeovers.
Applied's Splinter recently reiterated that its offer to buy part of ASM International (Bilthoven, the Netherlands) was "full and fair." Late last month, ASMI rejected the unsolicited offer from Applied Materials and private-equity firm Francisco Partners to acquire all of ASMI's front-end businesses for up to $800 million.
Chip-equipment maker Axcelis Technologies Inc. (Beverly, Mass.) said that the company, Japan's Sumitomo Heavy Industries Ltd. (SHI) and private-equity firm TPG Capital have entered into a ''confidentiality agreement'' with respect to discussions between the parties. The companies did not elaborate, but for some time, SHI and TPG have made various unsolicited offers to acquire Axcelis.
Contrary to popular belief, Aquest Systems Corp. has not given up on its efforts to acquire Asyst Technologies Inc. Fab-tool automation firm Asyst recently announced that it had received notice from Riley Investment Partners Master Fund L.P., a hedge fund that with related parties claims to own 2.6 percent of Asyst's outstanding shares.
Riley intends to nominate six directors for election at the company's 2008 annual meeting in an attempt to gain control of Asyst's board. Riley's notice stated that its nominees, if elected, intend to sell the company through an auction process.
Adding to the intrigue, Aquest is an investor in Riley, said Mihir Parikh, president and CEO of Aquest. Parikh was also the founder of Asyst and its CEO from its inception in 1984 until 2002. And if or when Asyst goes up for sale, Aquest will be one of the bidders, he said.
The semiconductor-equipment market was already in the midst of a slowdown amid what some call a ''disconnect'' in the sector. Fab utilization rates remain high, but capital spending is down by some 20-to-25 percent due to a lull in ICs.
Compounding the ''disconnect'' at Semicon West is a solar event, which is running in tandem at the show. While there is a buzz at the Intersolar event, the semiconductor fab-tool portion of the show is relatively quiet, with vendors grumbling about the lack of foot traffic in their booths.
Reports that Samsung is now putting the brakes on its capital spending exacerbated the doom-and-gloom sentiment. Samsung is the world's largest buyer of capital equipment, surpassing Intel Corp. several years ago, it was noted.
Amid the Samsung rumors, many are beginning to whisper the ''D'' word: downturn. Still others say it's much worse and calling it a depression.
The net effect: Expect an acceleration of the ongoing shakeout in the fab-tool and electronics materials industries. The strong will get stronger and the weak will not survive over the long haul.
Which companies are the next takeover targets? Axcelis, ASMI and Asyst are currently fending off unfriendly takeover bids. Perhaps some big-name players--Lam, Novellus and Varian--are in play. Most certainty, the new startups will be the first takeover targets.
Clearly, the landscape will change--again. Indeed, the current outlook reminds many of the severe and deep downturn in 2001. The semiconductor-equipment market is projected to hit $34.12 billion in 2008, down 20 percent over 2007, according to SEMI.
In comparison, the fab-tool market grew by 6 percent in 2007, according to SEMI (San Jose, Calif.). Following the downturn in 2008, the semiconductor-equipment market is projected to rebound with annual growth of 13 percent and 6 percent in 2009 and 2010, respectively, according to the trade group.
The poor climate in 2008 is due to ''lower spending in the memory sector and a less than favorable device pricing environment,'' said Stanley Myers, president and CEO, of SEMI at a press event.
Capital spending in the memory sector is especially troublesome, said Rick Hill, president and chief executive of Novellus Systems Inc. (San Jose, Calif.) "No one can argue that memory is under pressure,'' Hill said during the company's analyst meeting. "Do I think the market will get better when I wake up in the morning? Hell no. I need Maalox every morning.''
In addition to the business woes, the U.S. sub-prime mortgage crisis and soaring oil prices ''creates uncertainties'' in the overall economy, thereby impacting consumer spending for electronic goods, said Harvey Frye, president of Tokyo Electron America Inc. (Austin, Texas). Tokyo Electron America is the U.S. subsidiary of Japanese semiconductor equipment giant Tokyo Electron Ltd. (TEL).
A poor memory environment, coupled with economic woes, spells bad news for vendors. ''This is a big downturn," declared Mike Splinter, president and CEO of Applied Materials Inc. (Santa Clara, Calif.), at the company's analyst meeting.
Overall, semiconductor equipment is a ''tough market," he said. Originally, Applied projected that the front-end equipment market would fall by 5-to-15 percent in 2008 over 2007. Now, the world's largest equipment vendor projects that the wafer-fab equipment segment could fall bt 25-to-30 percent this year, he said.
On the bright side, flat-panel displays are still growing and capital spending could jump by 30 percent in 208. "Capex has been bigger than what we expected,'' he said.
Applied, which has made a number of acquisitions in the solar-gear market, also sees strong growth in that business. The company ''has not caught up'' with demand for solar gear, he added.
2009 forecast
Going forward, some see a slight recovery in 2009. Others see a prolonged downturn.
Much of the recovery hinges on the memory market. But a recovery ''is hard to predict,'' said Brian Trafas, chief marketing officer at KLA-Tencor Corp. (San Jose, Calif.). "Until we see an uptick in memory pricing, it's hard to see any capacity buys.''
"2009 looks like a flattish year," said Jerry Cutini, president and CEO of Aviza Technology Inc. (Scotts Valley, Calif.) ''Flat would be considered good in 2009.''
2009 could take a turn for the worse--if, say, oil prices continue to soar. "If oil goes to $200 a barrel, it's going to be a bad year,'' he said.
During a presentation, Tom St. Dennis, senior vice president and general manager of the Silicon Systems Group at Applied Materials, listed several drivers that could bring the industry out of its slump. Among the major drivers are DDR3 memory, solid-state storage drives, and next-generation communications and graphics chips, he said.
What is clear that the landscape will change in semiconductor equipment. For example, no less than three vendors are fighting off hostile takeovers.
Applied's Splinter recently reiterated that its offer to buy part of ASM International (Bilthoven, the Netherlands) was "full and fair." Late last month, ASMI rejected the unsolicited offer from Applied Materials and private-equity firm Francisco Partners to acquire all of ASMI's front-end businesses for up to $800 million.
Chip-equipment maker Axcelis Technologies Inc. (Beverly, Mass.) said that the company, Japan's Sumitomo Heavy Industries Ltd. (SHI) and private-equity firm TPG Capital have entered into a ''confidentiality agreement'' with respect to discussions between the parties. The companies did not elaborate, but for some time, SHI and TPG have made various unsolicited offers to acquire Axcelis.
Contrary to popular belief, Aquest Systems Corp. has not given up on its efforts to acquire Asyst Technologies Inc. Fab-tool automation firm Asyst recently announced that it had received notice from Riley Investment Partners Master Fund L.P., a hedge fund that with related parties claims to own 2.6 percent of Asyst's outstanding shares.
Riley intends to nominate six directors for election at the company's 2008 annual meeting in an attempt to gain control of Asyst's board. Riley's notice stated that its nominees, if elected, intend to sell the company through an auction process.
Adding to the intrigue, Aquest is an investor in Riley, said Mihir Parikh, president and CEO of Aquest. Parikh was also the founder of Asyst and its CEO from its inception in 1984 until 2002. And if or when Asyst goes up for sale, Aquest will be one of the bidders, he said.
Achieve PCIe compliance and interoperability in your IP core-based design
Since its inception more than five years ago, PCIe technology has become the dominant interconnect protocol across virtually all market segments. Today, all of the major chipset vendors are implementing PCIe technology into their chipsets.
The quick adoption of PCIe technology has resulted in a market flooded with many different implementations of the PCIe specification. While, theoretically, each of these implementations should be compliant with the specification and interoperate with all other implementations, the reality is that non-compliant and non-interoperable devices do make their way to the marketplace.
When one considers the high cost of fixing a non-compliant or non-interoperable device once it reaches silicon, much less once it has been released to the market, assuring pre-silicon compliance and interoperability of a device becomes one of the most important challenges to any PCIe development process.
Recognizing this enormous cost, the EDA industry has come forth with a myriad of solutions capable of managing this obstacle. These solutions include advanced verification and assertion languages, functional coverage tools, and protocol specific models and compliance test suites.
Given the wide range of solutions made available by the EDA industry, selecting the best solution to assure pre-silicon compliance and interoperability of a device requires a thorough understanding of the issues that cause devices to be deemed noncompliant or non-interoperable.
Challenges
As one reads the PCIe Base Specification, or any specification for that matter, assumptions are made as to how the device is intended to behave.
Although standards bodies such as the PCI-Special Interest Group (SIG) take great strides to remove all ambiguity from their specifications, these specifications remain open to interpretation, and assumptions are made as developers read the specification.
In the best-case scenario, these assumptions are consistent amongst developers and with the intent of the author of the specification, whom in this case is the PCI-SIG. In reality, this consistency is often absent. More commonly, differing assumptions exist between developers.
In this case, the resolution of these differences comes only after extensive discussions, which oftentimes require the guidance of the author of the specification.
In the worst-case scenario, all developers make the same assumptions, which are, unfortunately, inconsistent with the intent of the author of the specification. In this case, the resulting device does not match the intent of the specification.
Therefore, it is critical for any pre-silicon compliance solution to have identified and resolved all assumptions made in the development of the said solution.
Assumptions are identified and resolved as more developers review and use the solution. The result is that as a solution gains wider acceptance in the industry, more confidence can be placed in the accuracy of the solution.
As devices continue to grow in size and complexity, the task of enumerating, much less verifying, all possible scenarios becomes extremely difficult. And it becomes increasingly probable that some features of the device will not be covered in the verification process.
Although the PCIe specification details hundreds of registers, multiple complex state machines and a plethora of optional functionality, this is not an issue unique to the PCIe specification.
In response to this industry-wide issue, coverage-driven verification methodologies have been developed and successfully proven. These methodologies generally involve the placement of assertions into the device and the verification environment.
Once the assertions are placed, random stimulus is applied to the device, and coverage statistics are collected. As such, to be useful in a coverage-driven verification methodology, any pre-silicon compliance solution must include a robust set of assertions, along with a facility for the collection of coverage statistics.
Verifying IP cores
With the rapid adoption of PCIe technology, PCIe design cores are quickly becoming commodity parts. Generally, there is little value to be added to a device by building a PCIe design core from scratch when a wide variety of PCIe design cores are available from many vendors, each offering its own set of features.
Ideally, all PCIe design cores on the market should be bug-free; however, that is not always the case. Therefore, the challenge for any development team using a PCIe design core is to determine how to deal with a core that has presumably been verified.
Most development teams either do not have or do not wish to allocate resources to the verification of a pre-verified PCIe design core.
As such, a presilicon compliance solution that provides a complete, self-contained verification environment is instrumental in filling this gap, provided the solution can be easily integrated with the device.
Additionally, given the limited resources generally applied to this task, any issues identified by the solution must be easily debugged and resolved.
Interoperability testing
Interoperability is defined as the ability of a device to communicate with all other devices. In the PCIe domain, this implies that two devices are interoperable if, and only if, the devices can correctly manage their connection and exchange transactions.
For a device to be fully interoperable, it must be able to do this with all possible devices on the market. Interoperability in a pre-silicon environment is extremely difficult. Indirect interoperability is an alternative option.
The concept of indirect interoperability states that, given three devices, if the first two devices are known to interoperate with the third device, then the first two should be interoperable with each other (Figure 1, above ).
Applying this concept, a pre-silicon compliance solution provides an assurance that the device will be interoperable with all other devices using the same solution (Figure 2 below).
As a given solution gains wider acceptance throughout the industry and is used to assure pre-silicon compliance with a wider array of devices, this wider array of devices will be known to interoperate with each other.
As the cost of a silicon re-spin grows with each passing day, it becomes critical to assure pre-silicon compliance and interoperability for all PCIe devices. The sources of compliance and interoperability bugs are complex and often go unnoticed.
The only way to mitigate the risk of producing a non-compliant or non-interoperable device is to address each of these sources with a widely accepted and easily integrated solution containing advanced verification features.
Joshua Filliater is an Applications Engineer at Denali Software, Inc.
The quick adoption of PCIe technology has resulted in a market flooded with many different implementations of the PCIe specification. While, theoretically, each of these implementations should be compliant with the specification and interoperate with all other implementations, the reality is that non-compliant and non-interoperable devices do make their way to the marketplace.
When one considers the high cost of fixing a non-compliant or non-interoperable device once it reaches silicon, much less once it has been released to the market, assuring pre-silicon compliance and interoperability of a device becomes one of the most important challenges to any PCIe development process.
Recognizing this enormous cost, the EDA industry has come forth with a myriad of solutions capable of managing this obstacle. These solutions include advanced verification and assertion languages, functional coverage tools, and protocol specific models and compliance test suites.
Given the wide range of solutions made available by the EDA industry, selecting the best solution to assure pre-silicon compliance and interoperability of a device requires a thorough understanding of the issues that cause devices to be deemed noncompliant or non-interoperable.
Challenges
As one reads the PCIe Base Specification, or any specification for that matter, assumptions are made as to how the device is intended to behave.
Although standards bodies such as the PCI-Special Interest Group (SIG) take great strides to remove all ambiguity from their specifications, these specifications remain open to interpretation, and assumptions are made as developers read the specification.
In the best-case scenario, these assumptions are consistent amongst developers and with the intent of the author of the specification, whom in this case is the PCI-SIG. In reality, this consistency is often absent. More commonly, differing assumptions exist between developers.
In this case, the resolution of these differences comes only after extensive discussions, which oftentimes require the guidance of the author of the specification.
In the worst-case scenario, all developers make the same assumptions, which are, unfortunately, inconsistent with the intent of the author of the specification. In this case, the resulting device does not match the intent of the specification.
Therefore, it is critical for any pre-silicon compliance solution to have identified and resolved all assumptions made in the development of the said solution.
Assumptions are identified and resolved as more developers review and use the solution. The result is that as a solution gains wider acceptance in the industry, more confidence can be placed in the accuracy of the solution.
As devices continue to grow in size and complexity, the task of enumerating, much less verifying, all possible scenarios becomes extremely difficult. And it becomes increasingly probable that some features of the device will not be covered in the verification process.
Although the PCIe specification details hundreds of registers, multiple complex state machines and a plethora of optional functionality, this is not an issue unique to the PCIe specification.
In response to this industry-wide issue, coverage-driven verification methodologies have been developed and successfully proven. These methodologies generally involve the placement of assertions into the device and the verification environment.
Once the assertions are placed, random stimulus is applied to the device, and coverage statistics are collected. As such, to be useful in a coverage-driven verification methodology, any pre-silicon compliance solution must include a robust set of assertions, along with a facility for the collection of coverage statistics.
Verifying IP cores
With the rapid adoption of PCIe technology, PCIe design cores are quickly becoming commodity parts. Generally, there is little value to be added to a device by building a PCIe design core from scratch when a wide variety of PCIe design cores are available from many vendors, each offering its own set of features.
Ideally, all PCIe design cores on the market should be bug-free; however, that is not always the case. Therefore, the challenge for any development team using a PCIe design core is to determine how to deal with a core that has presumably been verified.
Most development teams either do not have or do not wish to allocate resources to the verification of a pre-verified PCIe design core.
As such, a presilicon compliance solution that provides a complete, self-contained verification environment is instrumental in filling this gap, provided the solution can be easily integrated with the device.
Additionally, given the limited resources generally applied to this task, any issues identified by the solution must be easily debugged and resolved.
Interoperability testing
Interoperability is defined as the ability of a device to communicate with all other devices. In the PCIe domain, this implies that two devices are interoperable if, and only if, the devices can correctly manage their connection and exchange transactions.
For a device to be fully interoperable, it must be able to do this with all possible devices on the market. Interoperability in a pre-silicon environment is extremely difficult. Indirect interoperability is an alternative option.
The concept of indirect interoperability states that, given three devices, if the first two devices are known to interoperate with the third device, then the first two should be interoperable with each other (Figure 1, above ).
Applying this concept, a pre-silicon compliance solution provides an assurance that the device will be interoperable with all other devices using the same solution (Figure 2 below).
As a given solution gains wider acceptance throughout the industry and is used to assure pre-silicon compliance with a wider array of devices, this wider array of devices will be known to interoperate with each other.
As the cost of a silicon re-spin grows with each passing day, it becomes critical to assure pre-silicon compliance and interoperability for all PCIe devices. The sources of compliance and interoperability bugs are complex and often go unnoticed.
The only way to mitigate the risk of producing a non-compliant or non-interoperable device is to address each of these sources with a widely accepted and easily integrated solution containing advanced verification features.
Joshua Filliater is an Applications Engineer at Denali Software, Inc.
Low power design for analog/mixed signal IP
Power reduction and management techniques using multiple clock and power domains, dynamic voltage and frequency scaling and power gating are effective for digital circuits but for analog design, lowering power consumption must be considered early in the design phase. Starting with the techniques for lowering the power consumption in analog circuits such as operational amplifiers, this article will then focus on low power design for high-speed serial interconnects. Different architectures for output drivers and methods such as level shifting, for ac-coupled systems such as PCIe, Serial ATA and XAUI will be discussed.
System designers are influencing the specifications of high speed serial interconnects and a good example of this can be seen with the emerging standards for the USB protocol: LPM and HSIC. USB is prevalent as the high-speed serial interconnect in portable devices such as smart phones and mobile Internet devices. The goal of link power management (LPM) is to reduce power consumption of USB devices and hosts, potentially extending battery life by at least 20 percent. HSIC or "high speed inter-chip USB" allows low power high-speed data transfers (480Mbit/s) using a source synchronous clocked serial interface. Both will be reviewed in this article.
Back to basics: The op amp
In the design of analog/mixed-signal IP many factors contribute to the overall consumption of power. The common methods include:
Simplifying the complexity of the circuit and using folded designs exploiting the complementary properties of NMOS and PMOS devices.
Taking conventional architectures and converting them into designs that consume less power with adaptive biasing.
Gearing the integrated circuit technology towards low power performance by using high Vt processes for example 65nm LP or 40nm LP. Although this may not necessarily reduce power in the active mode as more current is needed to drive the high-speed transmitter in the slower, low power technologies.
Decreasing transistor dimensions together with lowering the supply voltage.
Before delving into power reduction techniques for high speed serial interfaces, consider the case of an operational amplifier as the techniques applied here are pertinent to many other circuit examples.
1. The power consumption of the operational amplifier can be reduced by use of an architecture with only a single (differential) stage. This will reduce the current consumption of the device. However, a method of maximizing the gain, while preserving an acceptable bandwidth and slew rate are now required in the single gain stage.
2. The output stage could be designed to provide sufficient output drive while quiescently consuming as little power as possible.
3. Optimizing the biasing circuit will reduce the power consumption in the op-amp. This is achieved by reducing the internal stage currents by programming an external current in the form of a resistor outside the integrated circuit. Speed, voltage noise and junction leakage will now become major considerations for the designer as these parameters are affected by the value of the bias current programmed.
4. Two important factors that determine the maximum power dissipation in an integrated circuit are the technology used for the design and the type of application. A particular application for CMOS op-amps could be low power switched capacitor filters. If a lower power/low leakage CMOS technology such as 65LP or 40LP is used, then there are two important requirements in the op-amp design. First there must be enough current to charge the compensation capacitor and load capacitor in the required time. Second there must be enough current in the second gain stage transistor to maintain a phase margin of 45 to avoid ringing and degradation of the settling time. If the output current of this circuit is less than the quiescent bias current then this is known as a Class A circuit.
5. Quiescent power dissipation can be reduced by replacing Class A op-amps with Class AB and dynamic op-amps. The Class AB output stage is designed to be biased at small currents so quiescent power dissipation is correspondingly lower.
6. The basic two-stage differential input op-amp can be designed in the sub-threshold current region to minimize the current consumption.
Scaling issues: Is analog anti-Moore?
Whereas scaling of digital circuits is has been investigated in detail, the application of scaling analog circuits is still not that common. For example typical transistor dimensions in an analog circuit are a few multiples larger than 40nm minimum channels.
The sub-threshold characteristics of devices with channel lengths below 2m are very different to devices with larger dimensions. It has been observed that the current becomes exponentially dependent on drain voltage independent of VDS. This effect is sometimes referred to as "drain induced barrier lowering" (DIBL). If this effect can be avoided then IDdecreases exponentially as VGS is reduced below VT.
Scaling devices, and reducing the supply voltage accordingly, will not degrade open circuit voltage gain. Scaling dimensions but keeping supply voltage constant will, however, decrease the gain. The dynamic range of circuits such as op-amps fall because the analog signal range becomes limited due to the reduction in the power supply voltage. The problems of scaling down include fabrication challenges, limitations in the design of devices and circuits and the efficiency and distribution of power supplies.
Thermal noise will remain constant because the device transconductance remains constant under constant field scaling. The 1/f noise intensifies, but the effect of this can be reduced by translating the signal to a higher portion of the frequency spectrum, using chopper stabilization.
Low power guidelines
A set of guidelines can be developed for low power analog design, considering the op-amp as an example: the biasing circuitry, input, output and compensation stages can be examined.
The DC biasing circuitry for the op-amp must provide accurately determined and suitably regulated quiescent biasing currents at very low current levels. The current must be insensitive to changes in temperature, supply voltage and process tolerances.
The configuration of the input stage will dictate whether the op-amp can be used in a single low voltage (1.2V, or lower) supply application. Therefore the following properties are desirable (but not always possible) on a particular low power analog design:
Very low power supply operation using core devices Class B or AB output stage " this reduces the quiescent power dissipation particularly in a leaky process A rail to rail common mode input range A load-capacitance aware compensation scheme Capability to drive a small output load Bandwidth and slew rate commensurate with supply current Getting high precision by keeping offsets low, high input impedance, high CMRR and high PSRR.
Low power design example
The following is an example of a low-power, high-speed driver used in a USB 2.0 PHY. Power is kept very low with the use of a voltage-mode driver, shown in Figure 1.
In fact, for AC-coupled systems such as PCIe, Serial ATA and XAUI, a voltage-mode driver draws 25 percent of the supply current of a current-mode implementation. For example, a classical USB 2.0 driver requires nominal amplitude of 400mV for high-speed data transmission into a 45 load. The static power dissipation from the supply for a current-mode driver is approximately 60mW. Whereas, the power dissipation from the supply for a voltage-mode driver is approximately 30mW.
Another power-reduction technique is to optimize by level shifting down into the low-voltage core device domain as early as possible in the signal path so that device characteristics are leveraged as much as possible in order to reduce power. This strategy enables most high-frequency analog signal processing to be done in the low-voltage domain (for example in the USB, high-speed squelch detection and high speed receive function are implemented using low voltage core devices).
Low-power design is also important in sleep modes (non-functional modes) especially for mobile devices. For example, in the USB protocol the PHY can be held in suspend mode for long periods of time. As a result the power dissipation in this mode can become a significant portion of the total and must be scaled aggressively.
Power gating in digital circuits is often used where more aggressive power reduction is necessary. Power gating helps reduce both channel and gate leakage by collapsing the supply and eliminating the leakage current path. This can be implemented on a sub-block level by implementing collapsible, thick-oxide regulators that can be disabled in low-power modes.
Digital supply leakage often dominates the power down current and so many SoC's collapse the digital (core) supply rail in these modes as well. Doing so can cause serious side effects as analog level-shifters found in MSIP can often cause excessive current draw. Special care in the design of level shifters found in MSIP is necessary to avoid this. One example includes circuitry that detects when the digital power supply is collapsed; the circuitry then presets the analog control signals to the IDDQ state thereby eliminating unwanted leakage current.
Emerging low power standards for USB
For portable devices system designers are looking at ways to reduce power and one area where power can be saved is using low power versions of USB. Two standards are emerging: "Link Power Management" (LPM) and "High Speed Inter-chip USB" (HSIC).
LPM defines a new power sleep state between enable and suspend thereby conserving more power than the present suspend/resume mode. Also sleep mode occurs more often and faster reducing the transitional power states by three orders of magnitude. This reduces power consumption of USB devices and hosts and potentially extending battery life by at least 20 percent of the portable device.
HSIC is USB without the cable or the connector. It allows low power high-speed data transfers (480Mbit/s) using a source synchronous clocked serial interface. Low power is achieved with 1.2V LVCMOS signaling levels that is there no 3.3V signaling.
Summary
Novel circuit techniques can be used to reduce power significantly—enabling integration in very low-power mobile applications. Power reduction techniques include investigating the following:
1. Transmitter architectures 2. Analog signal processing in low-voltage domain 3. Sleep mode power reduction
Technology choice can impact power consumption although an LP technology may not necessarily give the lowest power for high speed serial interconnects. From a systems perspective applications that need to support low power embedded designs and portable devices such as smart phones and mobile internet devices will require new standards such as LPM and HSIC.
References:
"Building High-Quality, Mixed-Signal IP in 65-nm and Beyond" by Chong, Lam, Nandra, Toffolon, IP07, December 2007.
About the author
Navraj Nandra is director of product marketing for the mixed-signal products that include SERDES, USB and DDR2. Navraj holds a masters degree in Microelectronics, majoring in analog IC design, from Brunel University and a post-graduate diploma in Process Technology from Middlesex University.
System designers are influencing the specifications of high speed serial interconnects and a good example of this can be seen with the emerging standards for the USB protocol: LPM and HSIC. USB is prevalent as the high-speed serial interconnect in portable devices such as smart phones and mobile Internet devices. The goal of link power management (LPM) is to reduce power consumption of USB devices and hosts, potentially extending battery life by at least 20 percent. HSIC or "high speed inter-chip USB" allows low power high-speed data transfers (480Mbit/s) using a source synchronous clocked serial interface. Both will be reviewed in this article.
Back to basics: The op amp
In the design of analog/mixed-signal IP many factors contribute to the overall consumption of power. The common methods include:
Simplifying the complexity of the circuit and using folded designs exploiting the complementary properties of NMOS and PMOS devices.
Taking conventional architectures and converting them into designs that consume less power with adaptive biasing.
Gearing the integrated circuit technology towards low power performance by using high Vt processes for example 65nm LP or 40nm LP. Although this may not necessarily reduce power in the active mode as more current is needed to drive the high-speed transmitter in the slower, low power technologies.
Decreasing transistor dimensions together with lowering the supply voltage.
Before delving into power reduction techniques for high speed serial interfaces, consider the case of an operational amplifier as the techniques applied here are pertinent to many other circuit examples.
1. The power consumption of the operational amplifier can be reduced by use of an architecture with only a single (differential) stage. This will reduce the current consumption of the device. However, a method of maximizing the gain, while preserving an acceptable bandwidth and slew rate are now required in the single gain stage.
2. The output stage could be designed to provide sufficient output drive while quiescently consuming as little power as possible.
3. Optimizing the biasing circuit will reduce the power consumption in the op-amp. This is achieved by reducing the internal stage currents by programming an external current in the form of a resistor outside the integrated circuit. Speed, voltage noise and junction leakage will now become major considerations for the designer as these parameters are affected by the value of the bias current programmed.
4. Two important factors that determine the maximum power dissipation in an integrated circuit are the technology used for the design and the type of application. A particular application for CMOS op-amps could be low power switched capacitor filters. If a lower power/low leakage CMOS technology such as 65LP or 40LP is used, then there are two important requirements in the op-amp design. First there must be enough current to charge the compensation capacitor and load capacitor in the required time. Second there must be enough current in the second gain stage transistor to maintain a phase margin of 45 to avoid ringing and degradation of the settling time. If the output current of this circuit is less than the quiescent bias current then this is known as a Class A circuit.
5. Quiescent power dissipation can be reduced by replacing Class A op-amps with Class AB and dynamic op-amps. The Class AB output stage is designed to be biased at small currents so quiescent power dissipation is correspondingly lower.
6. The basic two-stage differential input op-amp can be designed in the sub-threshold current region to minimize the current consumption.
Scaling issues: Is analog anti-Moore?
Whereas scaling of digital circuits is has been investigated in detail, the application of scaling analog circuits is still not that common. For example typical transistor dimensions in an analog circuit are a few multiples larger than 40nm minimum channels.
The sub-threshold characteristics of devices with channel lengths below 2m are very different to devices with larger dimensions. It has been observed that the current becomes exponentially dependent on drain voltage independent of VDS. This effect is sometimes referred to as "drain induced barrier lowering" (DIBL). If this effect can be avoided then IDdecreases exponentially as VGS is reduced below VT.
Scaling devices, and reducing the supply voltage accordingly, will not degrade open circuit voltage gain. Scaling dimensions but keeping supply voltage constant will, however, decrease the gain. The dynamic range of circuits such as op-amps fall because the analog signal range becomes limited due to the reduction in the power supply voltage. The problems of scaling down include fabrication challenges, limitations in the design of devices and circuits and the efficiency and distribution of power supplies.
Thermal noise will remain constant because the device transconductance remains constant under constant field scaling. The 1/f noise intensifies, but the effect of this can be reduced by translating the signal to a higher portion of the frequency spectrum, using chopper stabilization.
Low power guidelines
A set of guidelines can be developed for low power analog design, considering the op-amp as an example: the biasing circuitry, input, output and compensation stages can be examined.
The DC biasing circuitry for the op-amp must provide accurately determined and suitably regulated quiescent biasing currents at very low current levels. The current must be insensitive to changes in temperature, supply voltage and process tolerances.
The configuration of the input stage will dictate whether the op-amp can be used in a single low voltage (1.2V, or lower) supply application. Therefore the following properties are desirable (but not always possible) on a particular low power analog design:
Very low power supply operation using core devices Class B or AB output stage " this reduces the quiescent power dissipation particularly in a leaky process A rail to rail common mode input range A load-capacitance aware compensation scheme Capability to drive a small output load Bandwidth and slew rate commensurate with supply current Getting high precision by keeping offsets low, high input impedance, high CMRR and high PSRR.
Low power design example
The following is an example of a low-power, high-speed driver used in a USB 2.0 PHY. Power is kept very low with the use of a voltage-mode driver, shown in Figure 1.
In fact, for AC-coupled systems such as PCIe, Serial ATA and XAUI, a voltage-mode driver draws 25 percent of the supply current of a current-mode implementation. For example, a classical USB 2.0 driver requires nominal amplitude of 400mV for high-speed data transmission into a 45 load. The static power dissipation from the supply for a current-mode driver is approximately 60mW. Whereas, the power dissipation from the supply for a voltage-mode driver is approximately 30mW.
Another power-reduction technique is to optimize by level shifting down into the low-voltage core device domain as early as possible in the signal path so that device characteristics are leveraged as much as possible in order to reduce power. This strategy enables most high-frequency analog signal processing to be done in the low-voltage domain (for example in the USB, high-speed squelch detection and high speed receive function are implemented using low voltage core devices).
Low-power design is also important in sleep modes (non-functional modes) especially for mobile devices. For example, in the USB protocol the PHY can be held in suspend mode for long periods of time. As a result the power dissipation in this mode can become a significant portion of the total and must be scaled aggressively.
Power gating in digital circuits is often used where more aggressive power reduction is necessary. Power gating helps reduce both channel and gate leakage by collapsing the supply and eliminating the leakage current path. This can be implemented on a sub-block level by implementing collapsible, thick-oxide regulators that can be disabled in low-power modes.
Digital supply leakage often dominates the power down current and so many SoC's collapse the digital (core) supply rail in these modes as well. Doing so can cause serious side effects as analog level-shifters found in MSIP can often cause excessive current draw. Special care in the design of level shifters found in MSIP is necessary to avoid this. One example includes circuitry that detects when the digital power supply is collapsed; the circuitry then presets the analog control signals to the IDDQ state thereby eliminating unwanted leakage current.
Emerging low power standards for USB
For portable devices system designers are looking at ways to reduce power and one area where power can be saved is using low power versions of USB. Two standards are emerging: "Link Power Management" (LPM) and "High Speed Inter-chip USB" (HSIC).
LPM defines a new power sleep state between enable and suspend thereby conserving more power than the present suspend/resume mode. Also sleep mode occurs more often and faster reducing the transitional power states by three orders of magnitude. This reduces power consumption of USB devices and hosts and potentially extending battery life by at least 20 percent of the portable device.
HSIC is USB without the cable or the connector. It allows low power high-speed data transfers (480Mbit/s) using a source synchronous clocked serial interface. Low power is achieved with 1.2V LVCMOS signaling levels that is there no 3.3V signaling.
Summary
Novel circuit techniques can be used to reduce power significantly—enabling integration in very low-power mobile applications. Power reduction techniques include investigating the following:
1. Transmitter architectures 2. Analog signal processing in low-voltage domain 3. Sleep mode power reduction
Technology choice can impact power consumption although an LP technology may not necessarily give the lowest power for high speed serial interconnects. From a systems perspective applications that need to support low power embedded designs and portable devices such as smart phones and mobile internet devices will require new standards such as LPM and HSIC.
References:
"Building High-Quality, Mixed-Signal IP in 65-nm and Beyond" by Chong, Lam, Nandra, Toffolon, IP07, December 2007.
About the author
Navraj Nandra is director of product marketing for the mixed-signal products that include SERDES, USB and DDR2. Navraj holds a masters degree in Microelectronics, majoring in analog IC design, from Brunel University and a post-graduate diploma in Process Technology from Middlesex University.
Indian tech firms eye semi IP business
Indian technology companies facing cost pressures from a global economic slump and domestic competition are seeking a way out by boosting R&D investments to develop semiconductor intellectual property.
Ittiam Systems and Cosmic Circuits are pursuing the pure IP route, having rejected the services business; service providers Wipro and Mindtree are now developing chip IP and are using it to attract new services around their IP products.
Ittiam Systems is India's largest pure IP company, focusing on advanced media communication applications for which software solutions are either unavailable or too expensive. Its IP includes synthesizable RTL cores that can be integrating into an ASIC being designed by its customers.
In 2005, Ittiam began investing in multi-format high-definition video decoder IP. The video decoder can handle most video standards, enabling SoCs for HDTV and HD-DVD applications," said Srini Rajam, Ittiam's chairman and CEO.
"Venture funds and investors believe that IP companies cannot scale in revenue," said Ganapathy Subramaniam, CEO of Cosmic Circuits, an analog semiconductor IP company. "ARM and Rambus have proven them wrong. But it is also a fact that while there are many IP companies in the world, only very few of them have been able to scale in revenue."
Cosmic has created over 75 analog IP cores for portable power management, video analog front-end, WLAN and WiMax analog front-ends. The company works with more than 10 foundries to create IP cores from 0.35 nm to 65 nm.
"India is slowly emerging from services and getting into the business model of licensing IPs," Subramaniam added.
Market researcher Gartner Inc. ranks Wipro-NewLogic as the leading global provider of WLAN and Bluetooth IP, estimating that it holds two-thirds of the global market for IEEE 1394 IP cores. Wipro's chip IP arm is focusing on wireless and wireline connectivity.
"Developing IP is an important differentiation for the leading design service houses and...wireless communication, analog components and DSP-based IPs are the areas of promise for Indian companies," said A. Vasudevan, vice president of semiconductor and system solutions at Wipro Technologies.
Mindtree Ltd., which specializes in short-range wireless technologies, said it is focusing on Bluetooth IP. It has invested in ultrawideband technology, and plans to offer UWB IP in future products, according to S.N. Padmanabhan, senior vice president for semiconductors at Mindtree.
Mindtree also has several peripheral IP blocks usually bundled with the Bluetooth or UWB products. "The entry barrier is very low if someone has to build synthesizable IP at the RTL level," Padmanabhan said. "The semiconductor industry needs various IPs [and] smaller players can provide small, standards-based, popular IP blocks." Building IP blocks is the easy part, he added, noting that "marketing them is the toughest."
Sridhar Mitta, who headed Wipro's unsuccessful IP startup EnThink, acknowledged that India's track record for IP development is not good. "The [lessons] of EnThink are that product or IP companies will not get attention in large service companies," he said. "Indian companies will see IP business as an adjunct to their service businesses."
Matta said the best opportunities for Indian success in IP development are in volume markets like PCs or cellphones. Adopting standards and creating new ones will also boost India's IP efforts.
Gartner forecasts that Indian IP development will be dominated by big chip makers here as well as independent IP providers. "Some of the independent Indian IP providers are Wipro, Cosmic Circuits, Mindtree and HelloSoft," said Ganesh Ramamoorthy, Gartners' principal research analyst for semiconductor IP and design.
Ittiam Systems and Cosmic Circuits are pursuing the pure IP route, having rejected the services business; service providers Wipro and Mindtree are now developing chip IP and are using it to attract new services around their IP products.
Ittiam Systems is India's largest pure IP company, focusing on advanced media communication applications for which software solutions are either unavailable or too expensive. Its IP includes synthesizable RTL cores that can be integrating into an ASIC being designed by its customers.
In 2005, Ittiam began investing in multi-format high-definition video decoder IP. The video decoder can handle most video standards, enabling SoCs for HDTV and HD-DVD applications," said Srini Rajam, Ittiam's chairman and CEO.
"Venture funds and investors believe that IP companies cannot scale in revenue," said Ganapathy Subramaniam, CEO of Cosmic Circuits, an analog semiconductor IP company. "ARM and Rambus have proven them wrong. But it is also a fact that while there are many IP companies in the world, only very few of them have been able to scale in revenue."
Cosmic has created over 75 analog IP cores for portable power management, video analog front-end, WLAN and WiMax analog front-ends. The company works with more than 10 foundries to create IP cores from 0.35 nm to 65 nm.
"India is slowly emerging from services and getting into the business model of licensing IPs," Subramaniam added.
Market researcher Gartner Inc. ranks Wipro-NewLogic as the leading global provider of WLAN and Bluetooth IP, estimating that it holds two-thirds of the global market for IEEE 1394 IP cores. Wipro's chip IP arm is focusing on wireless and wireline connectivity.
"Developing IP is an important differentiation for the leading design service houses and...wireless communication, analog components and DSP-based IPs are the areas of promise for Indian companies," said A. Vasudevan, vice president of semiconductor and system solutions at Wipro Technologies.
Mindtree Ltd., which specializes in short-range wireless technologies, said it is focusing on Bluetooth IP. It has invested in ultrawideband technology, and plans to offer UWB IP in future products, according to S.N. Padmanabhan, senior vice president for semiconductors at Mindtree.
Mindtree also has several peripheral IP blocks usually bundled with the Bluetooth or UWB products. "The entry barrier is very low if someone has to build synthesizable IP at the RTL level," Padmanabhan said. "The semiconductor industry needs various IPs [and] smaller players can provide small, standards-based, popular IP blocks." Building IP blocks is the easy part, he added, noting that "marketing them is the toughest."
Sridhar Mitta, who headed Wipro's unsuccessful IP startup EnThink, acknowledged that India's track record for IP development is not good. "The [lessons] of EnThink are that product or IP companies will not get attention in large service companies," he said. "Indian companies will see IP business as an adjunct to their service businesses."
Matta said the best opportunities for Indian success in IP development are in volume markets like PCs or cellphones. Adopting standards and creating new ones will also boost India's IP efforts.
Gartner forecasts that Indian IP development will be dominated by big chip makers here as well as independent IP providers. "Some of the independent Indian IP providers are Wipro, Cosmic Circuits, Mindtree and HelloSoft," said Ganesh Ramamoorthy, Gartners' principal research analyst for semiconductor IP and design.
ARM Mali-200 GPU World's First To Achieve Khronos OpenGL ES 2.0 Conformance At 1080p HDTV Resolution
July 14, 2008
WHAT: The ARM® Mali™-200 graphics processing unit is the first GPU on today’s market to pass Khronos conformance testing at up to 1080p HDTV resolutions. This brings accredited graphics acceleration to the broadest range of consumer devices, from next-generation set-top boxes to mobile devices with TV Out, to high-definition TVs. ARM is enabling its Partners to deliver attention-grabbing screen displays on all next-generation consumer electronics devices used at home and on the move.
ARM is dedicated to the support of open standards, enabling positive market growth, and the Mali-200 GPU demonstrates ARM’s continued technology leadership in graphics acceleration.
About ARM Mali Complete Graphics Stack
ARM delivers the most widely adopted graphics IP solutions, with 21 licensees of Mali graphics products and counting. ARM is the only vendor to provide a full range of graphics solutions, from the world’s smallest GPU to the highest performance GPU IP at more than one billion pixels per second, coupled with a complete stack of middleware and drivers and supported by a graphics ecosystem that harnesses the reach and power of the ARM Connected Community™.
WHY: The Khronos Group OpenGL ES 2.0 Conformance Tests, announced in May 2008, verify the OpenGL ES 2.0 API and its companion shader programming language, GLSL ES. Only once these tests are passed can a product be described as OpenGL ES 2.0 conformant.
WHEN: The Mali-200 GPU achieved conformance on July 12, 2008.
HOW: For more information about The Khronos Group and its conformance tests, please visit http://www.khronos.org/.
WHO: ARM designs the technology that lies at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM’s comprehensive product offering includes 32-bit RISC microprocessors, graphics processors, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company’s broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. More information on ARM is available at http://www.arm.com
WHAT: The ARM® Mali™-200 graphics processing unit is the first GPU on today’s market to pass Khronos conformance testing at up to 1080p HDTV resolutions. This brings accredited graphics acceleration to the broadest range of consumer devices, from next-generation set-top boxes to mobile devices with TV Out, to high-definition TVs. ARM is enabling its Partners to deliver attention-grabbing screen displays on all next-generation consumer electronics devices used at home and on the move.
ARM is dedicated to the support of open standards, enabling positive market growth, and the Mali-200 GPU demonstrates ARM’s continued technology leadership in graphics acceleration.
About ARM Mali Complete Graphics Stack
ARM delivers the most widely adopted graphics IP solutions, with 21 licensees of Mali graphics products and counting. ARM is the only vendor to provide a full range of graphics solutions, from the world’s smallest GPU to the highest performance GPU IP at more than one billion pixels per second, coupled with a complete stack of middleware and drivers and supported by a graphics ecosystem that harnesses the reach and power of the ARM Connected Community™.
WHY: The Khronos Group OpenGL ES 2.0 Conformance Tests, announced in May 2008, verify the OpenGL ES 2.0 API and its companion shader programming language, GLSL ES. Only once these tests are passed can a product be described as OpenGL ES 2.0 conformant.
WHEN: The Mali-200 GPU achieved conformance on July 12, 2008.
HOW: For more information about The Khronos Group and its conformance tests, please visit http://www.khronos.org/.
WHO: ARM designs the technology that lies at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM’s comprehensive product offering includes 32-bit RISC microprocessors, graphics processors, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company’s broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. More information on ARM is available at http://www.arm.com
Silicon Image Offers Mobile Phone Manufacturers a Better Way to Implement an HDTV Connection
Silicon Image, Inc., a leader in semiconductors and intellectual property for the secure storage, distribution and presentation of high-definition (HD) content, today announced its ultra-low-power interface solution consisting of a VastLane(TM) SiI9206 HDMI(TM) transmitter PHY semiconductor and a companion link layer IP core for use in consumer mobile device applications. This dual- mode solution supports the HDMI specification and Silicon Image's MHL(TM) technology interface.
MHL technology is a new connectivity solution that can dramatically reduce connector size by only requiring five pins for full HD content delivery. MHL technology can also accommodate multiple functions across shared pins like USB, charging, analog video and audio headsets, making it the most optimized answer for mobile handset requirements today.
"Consumers are demanding more from their mobile handsets as entertainment content becomes available for download and consumption. Connecting stored mobile content to an HDTV will be a differentiating handset feature," David Kuo, director of marketing at Silicon Image. "Taking high-resolution photos and storing full movies on your mobile handset is commonplace, and connecting to an HDTV is the perfect way to increase the value of that content."
The ultra-low-power SiI9206 PHY integrated circuit (IC), with built-in 8kV electro static discharge (ESD) protection, is ideal for mobile device applications and is designed to significantly reduce bill-of-material (BOM) costs. The link layer IP core, which is designed to be integrated into a system-on-a-chip (SoC), can be quickly targeted to any foundry or process, delivering a definite time-to-market advantage compared to a fully integrated solution. In addition, this implementation supports both HDMI and MHL technologies, enabling mobile device IC providers to support either interface in a single SoC design.
Today, mobile device IC providers have the option of either using external discrete HDMI chips or fully integrating HDMI functionality into their mobile device ICs. Silicon Image is now offering a solution that provides the benefits of both approaches, including a lower bill-of-material cost compared to discrete IC implementations, faster time-to-market and less chip I/O compared to full integration into the SoC.
"Our ultra-low-power dual-mode SiI9206 solution will enable consumers to play their high-quality mobile content at the full visual and audio capabilities of their HDTV systems," stated Ron Richter, director of business development at Silicon Image. "Silicon Image is the only provider of low-power HDMI ICs, full IP cores and the latest SiI9206 PHY IC approach that give our SoC customers the options they need to stay competitive in the mobile device and consumer electronics markets."
Key features of Silicon Image's HDMI/MHL transmitter PHY include:
Support for both HDMI and MHL technologies
Ultra-low power (<30mW at 1080p/30fps)
Low power down (<10mA)
Integrated 8kV ESD, reducing cost and board real estate
Small size (4mm x 4mm 28 pin QFN)
Broad operating temperature range (-20C to +85C)
Six-bit SoC data bus for reduced I/O (14 I/Os vs. 19 I/O-full HDMI integration)
Integrated CEC hardware support
Silicon Image plans to have samples of the SiI9206 transmitter PHY and the accompanying link layer IP core in the fourth quarter of 2008. More information on the company's transmitter IC and IP core solutions can be found at www.siliconimage.com.
Companies, engineers and developers interested in additional information should contact Ron Richter at 408-962-4259 or ron.richter@siliconimage.com.
About Silicon Image
Silicon Image, Inc. is a global leader in driving the architecture and semiconductor implementation for the secure storage, distribution and presentation of HD content in the consumer electronics, personal computing, and mobile device markets. With a rich history of technology innovation that includes creating industry standards such as DVI and HDMI, Silicon Image partners with the world's leading entertainment creators and electronics manufacturers to deliver digital HD content to consumers anytime, anywhere, on any device. Silicon Image is also a leading provider of semiconductor intellectual property solutions for HD multimedia and data storage applications. Additionally, Simplay Labs, LLC, a wholly-owned subsidiary of Silicon Image, offers robust testing tools, technologies, support services, consulting and product certification to electronics manufacturers to maximize performance, interoperability and ensure the highest-quality HD experience to consumers. With engineering, sales and customer support facilities located throughout North America, Asia and Europe, Silicon Image (NASDAQ: SIMG - News) is globally headquartered in Sunnyvale, California. For more information, please visit www.siliconimage.com.
MHL technology is a new connectivity solution that can dramatically reduce connector size by only requiring five pins for full HD content delivery. MHL technology can also accommodate multiple functions across shared pins like USB, charging, analog video and audio headsets, making it the most optimized answer for mobile handset requirements today.
"Consumers are demanding more from their mobile handsets as entertainment content becomes available for download and consumption. Connecting stored mobile content to an HDTV will be a differentiating handset feature," David Kuo, director of marketing at Silicon Image. "Taking high-resolution photos and storing full movies on your mobile handset is commonplace, and connecting to an HDTV is the perfect way to increase the value of that content."
The ultra-low-power SiI9206 PHY integrated circuit (IC), with built-in 8kV electro static discharge (ESD) protection, is ideal for mobile device applications and is designed to significantly reduce bill-of-material (BOM) costs. The link layer IP core, which is designed to be integrated into a system-on-a-chip (SoC), can be quickly targeted to any foundry or process, delivering a definite time-to-market advantage compared to a fully integrated solution. In addition, this implementation supports both HDMI and MHL technologies, enabling mobile device IC providers to support either interface in a single SoC design.
Today, mobile device IC providers have the option of either using external discrete HDMI chips or fully integrating HDMI functionality into their mobile device ICs. Silicon Image is now offering a solution that provides the benefits of both approaches, including a lower bill-of-material cost compared to discrete IC implementations, faster time-to-market and less chip I/O compared to full integration into the SoC.
"Our ultra-low-power dual-mode SiI9206 solution will enable consumers to play their high-quality mobile content at the full visual and audio capabilities of their HDTV systems," stated Ron Richter, director of business development at Silicon Image. "Silicon Image is the only provider of low-power HDMI ICs, full IP cores and the latest SiI9206 PHY IC approach that give our SoC customers the options they need to stay competitive in the mobile device and consumer electronics markets."
Key features of Silicon Image's HDMI/MHL transmitter PHY include:
Support for both HDMI and MHL technologies
Ultra-low power (<30mW at 1080p/30fps)
Low power down (<10mA)
Integrated 8kV ESD, reducing cost and board real estate
Small size (4mm x 4mm 28 pin QFN)
Broad operating temperature range (-20C to +85C)
Six-bit SoC data bus for reduced I/O (14 I/Os vs. 19 I/O-full HDMI integration)
Integrated CEC hardware support
Silicon Image plans to have samples of the SiI9206 transmitter PHY and the accompanying link layer IP core in the fourth quarter of 2008. More information on the company's transmitter IC and IP core solutions can be found at www.siliconimage.com.
Companies, engineers and developers interested in additional information should contact Ron Richter at 408-962-4259 or ron.richter@siliconimage.com.
About Silicon Image
Silicon Image, Inc. is a global leader in driving the architecture and semiconductor implementation for the secure storage, distribution and presentation of HD content in the consumer electronics, personal computing, and mobile device markets. With a rich history of technology innovation that includes creating industry standards such as DVI and HDMI, Silicon Image partners with the world's leading entertainment creators and electronics manufacturers to deliver digital HD content to consumers anytime, anywhere, on any device. Silicon Image is also a leading provider of semiconductor intellectual property solutions for HD multimedia and data storage applications. Additionally, Simplay Labs, LLC, a wholly-owned subsidiary of Silicon Image, offers robust testing tools, technologies, support services, consulting and product certification to electronics manufacturers to maximize performance, interoperability and ensure the highest-quality HD experience to consumers. With engineering, sales and customer support facilities located throughout North America, Asia and Europe, Silicon Image (NASDAQ: SIMG - News) is globally headquartered in Sunnyvale, California. For more information, please visit www.siliconimage.com.
Monday, July 14, 2008
Synopsys Broadens DesignWare SATA Solution With Device IP
Synopsys, Inc.
(Nasdaq: SNPS), a world leader in software and IP for semiconductor design
and manufacturing, today announced the availability of the DesignWare(R)
SATA Device IP, for use in applications such as solid state drives, hard
disk drives and optical disk drives. Additionally, Synopsys' comprehensive,
silicon-proven DesignWare SATA IP solution consisting of Device, Host, PHY
IP in 90 nanometer (nm) and 65nm processes, and Verification IP (VIP) has
passed the SATA-IO Building Block interoperability testing, demonstrating
full SATA functionality from a single vendor. Synopsys provides a
comprehensive high quality IP solution helping designers reduce the risk
and cost of integrating the SATA interface into their system-on-chip (SoC)
designs.
The Synopsys DesignWare SATA Device IP supports transfer speeds of 1.5
Gb/sec and 3.0 Gb/sec with a roadmap to 6Gb/sec, making it ideal for
storage applications requiring high system performance. A proven component
of the Synopsys Eclypse(TM) low power solution, the IP implements multiple
aggressive power management features which can be utilized to lower the
power consumption of the end application. The inclusion of a well-defined,
DMA-based software programming interface helps designers achieve optimal
system performance while maintaining low latency and minimal software
overhead. Furthermore, the supplied example firmware helps reduce the
overall software development, integration and maintenance effort.
With the release of the SATA Device IP, Synopsys now offers designers a
comprehensive, silicon-proven and fully interoperable SATA IP solution
consisting of the Device, Host, PHY and Verification IP. The DesignWare
SATA Host Controller supports Native Command Queuing and Asynchronous
Notification in up to eight ports. The Host Controller is verified with the
industry-standard AHCI software drivers provided as part of the Linux and
Microsoft Windows Vista operating systems, enabling designers to ease
system-level integration. Complementing the Host and Device Controllers is
the robust, low power DesignWare SATA PHY, which includes unique built-in
diagnostics allowing on-chip visibility into the link performance and ATE
test vectors for at-speed production testing. The DesignWare Verification
IP helps designers quickly and efficiently create a comprehensive
SATA-based environment. In addition, the SATA Verification IP delivers up
to 5X performance improvement when used with Synopsys' VCS(R) simulation
tool and is VMM-enabled to help speed the development of powerful
SystemVerilog testbenches.
"SATA International Organization (SATA-IO) commends our member
companies who are advancing SATA technology by introducing new products
that incorporate the advantages of this popular storage interface," said
Tom Pratt, SATA-IO board representative. "Fast transfer rates, low cost and
efficient protocol have made SATA the mainstream storage interface of
choice."
"The requirement for mass storage devices is continuing to grow, with
solid state drives estimated to increase at a 76 percent CAGR from 2007 to
2012 (1)," said John Koeter, senior director of marketing for IP and
Services at Synopsys. "By providing a complete DesignWare SATA IP solution
that offers a strong combination of proven interoperability, low power, and
ease of integration features, Synopsys enables designers to integrate the
SATA interface into SoC designs with less risk and improved time to
market."
Availability
The complete DesignWare SATA IP solution including Device, Host, PHY in
130nm, 90nm and 65nm processes, and Verification is available now. For more
information please visit: http://www.synopsys.com/sata_solutions/
In addition, on July 31 Synopsys will sponsor a free webinar titled,
"Achieving Optimal Performance and Low Power for SATA Device Designs" To
register, please go to: http://www.synopsys.com/sata/
About DesignWare IP
Synopsys offers a broad portfolio of high-quality, silicon-proven
digital, mixed-signal and verification IP for system-on-chip designs. As a
leading provider of connectivity IP, Synopsys delivers the industry's most
complete solutions for widely used protocols such as USB, PCI Express,
SATA, Ethernet and DDR. The DesignWare IP is optimized for low power and is
an integral part of the Synopsys Eclypse low power solution. In addition to
connectivity IP, Synopsys offers SystemC transaction level models to build
virtual platforms for rapid, pre-silicon development of software. When
combined with a robust IP development methodology, extensive investment in
quality and comprehensive technical support, DesignWare IP enables
designers to accelerate time-to-market and reduce integration risk. For
more information on DesignWare IP, visit http://www.synopsys.com/designware
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design
automation (EDA), supplying the global electronics market with the
software, intellectual property (IP) and services used in semiconductor
design and manufacturing. Synopsys' comprehensive, integrated portfolio of
implementation, verification, IP, manufacturing and field-programmable gate
array (FPGA) solutions helps address the key challenges designers and
manufacturers face today, such as power and yield management,
system-to-silicon verification and time-to-results. These
technology-leading solutions help give Synopsys customers a competitive
edge in bringing the best products to market quickly while reducing costs
and schedule risk. Synopsys is headquartered in Mountain View, California,
and has more than 60 offices located throughout North America, Europe,
Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.
(1) IDC, "Worldwide Solid State Drive 2008-2012 Forecast and Analysis:
Entering the No-Spin Zone," Doc # 212736, June 2008
Synopsys, DesignWare, Eclypse and VCS are registered trademarks or
trademarks of Synopsys, Inc. Any other trademarks or registered trademarks
mentioned in this release are the intellectual property of their respective
owners.
Editorial Contact:
Sheryl Gulizia
Synopsys, Inc.
650-584-8635
sgulizia@synopsys.com
Lisa Gillette-Martin
MCA, Inc.
650-968-8900 ext. 115
lgmartin@mcapr.com
(Nasdaq: SNPS), a world leader in software and IP for semiconductor design
and manufacturing, today announced the availability of the DesignWare(R)
SATA Device IP, for use in applications such as solid state drives, hard
disk drives and optical disk drives. Additionally, Synopsys' comprehensive,
silicon-proven DesignWare SATA IP solution consisting of Device, Host, PHY
IP in 90 nanometer (nm) and 65nm processes, and Verification IP (VIP) has
passed the SATA-IO Building Block interoperability testing, demonstrating
full SATA functionality from a single vendor. Synopsys provides a
comprehensive high quality IP solution helping designers reduce the risk
and cost of integrating the SATA interface into their system-on-chip (SoC)
designs.
The Synopsys DesignWare SATA Device IP supports transfer speeds of 1.5
Gb/sec and 3.0 Gb/sec with a roadmap to 6Gb/sec, making it ideal for
storage applications requiring high system performance. A proven component
of the Synopsys Eclypse(TM) low power solution, the IP implements multiple
aggressive power management features which can be utilized to lower the
power consumption of the end application. The inclusion of a well-defined,
DMA-based software programming interface helps designers achieve optimal
system performance while maintaining low latency and minimal software
overhead. Furthermore, the supplied example firmware helps reduce the
overall software development, integration and maintenance effort.
With the release of the SATA Device IP, Synopsys now offers designers a
comprehensive, silicon-proven and fully interoperable SATA IP solution
consisting of the Device, Host, PHY and Verification IP. The DesignWare
SATA Host Controller supports Native Command Queuing and Asynchronous
Notification in up to eight ports. The Host Controller is verified with the
industry-standard AHCI software drivers provided as part of the Linux and
Microsoft Windows Vista operating systems, enabling designers to ease
system-level integration. Complementing the Host and Device Controllers is
the robust, low power DesignWare SATA PHY, which includes unique built-in
diagnostics allowing on-chip visibility into the link performance and ATE
test vectors for at-speed production testing. The DesignWare Verification
IP helps designers quickly and efficiently create a comprehensive
SATA-based environment. In addition, the SATA Verification IP delivers up
to 5X performance improvement when used with Synopsys' VCS(R) simulation
tool and is VMM-enabled to help speed the development of powerful
SystemVerilog testbenches.
"SATA International Organization (SATA-IO) commends our member
companies who are advancing SATA technology by introducing new products
that incorporate the advantages of this popular storage interface," said
Tom Pratt, SATA-IO board representative. "Fast transfer rates, low cost and
efficient protocol have made SATA the mainstream storage interface of
choice."
"The requirement for mass storage devices is continuing to grow, with
solid state drives estimated to increase at a 76 percent CAGR from 2007 to
2012 (1)," said John Koeter, senior director of marketing for IP and
Services at Synopsys. "By providing a complete DesignWare SATA IP solution
that offers a strong combination of proven interoperability, low power, and
ease of integration features, Synopsys enables designers to integrate the
SATA interface into SoC designs with less risk and improved time to
market."
Availability
The complete DesignWare SATA IP solution including Device, Host, PHY in
130nm, 90nm and 65nm processes, and Verification is available now. For more
information please visit: http://www.synopsys.com/sata_solutions/
In addition, on July 31 Synopsys will sponsor a free webinar titled,
"Achieving Optimal Performance and Low Power for SATA Device Designs" To
register, please go to: http://www.synopsys.com/sata/
About DesignWare IP
Synopsys offers a broad portfolio of high-quality, silicon-proven
digital, mixed-signal and verification IP for system-on-chip designs. As a
leading provider of connectivity IP, Synopsys delivers the industry's most
complete solutions for widely used protocols such as USB, PCI Express,
SATA, Ethernet and DDR. The DesignWare IP is optimized for low power and is
an integral part of the Synopsys Eclypse low power solution. In addition to
connectivity IP, Synopsys offers SystemC transaction level models to build
virtual platforms for rapid, pre-silicon development of software. When
combined with a robust IP development methodology, extensive investment in
quality and comprehensive technical support, DesignWare IP enables
designers to accelerate time-to-market and reduce integration risk. For
more information on DesignWare IP, visit http://www.synopsys.com/designware
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design
automation (EDA), supplying the global electronics market with the
software, intellectual property (IP) and services used in semiconductor
design and manufacturing. Synopsys' comprehensive, integrated portfolio of
implementation, verification, IP, manufacturing and field-programmable gate
array (FPGA) solutions helps address the key challenges designers and
manufacturers face today, such as power and yield management,
system-to-silicon verification and time-to-results. These
technology-leading solutions help give Synopsys customers a competitive
edge in bringing the best products to market quickly while reducing costs
and schedule risk. Synopsys is headquartered in Mountain View, California,
and has more than 60 offices located throughout North America, Europe,
Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.
(1) IDC, "Worldwide Solid State Drive 2008-2012 Forecast and Analysis:
Entering the No-Spin Zone," Doc # 212736, June 2008
Synopsys, DesignWare, Eclypse and VCS are registered trademarks or
trademarks of Synopsys, Inc. Any other trademarks or registered trademarks
mentioned in this release are the intellectual property of their respective
owners.
Editorial Contact:
Sheryl Gulizia
Synopsys, Inc.
650-584-8635
sgulizia@synopsys.com
Lisa Gillette-Martin
MCA, Inc.
650-968-8900 ext. 115
lgmartin@mcapr.com
Thursday, July 10, 2008
Green Hills Software Delivers Layer 3 Routing for Freescale Multicore Processors
Green Hills Software has announced the availability of a secure, multicore-optimized networking and routing solution for the Freescale QorIQ™ processor portfolio. Based on the security and safety certified INTEGRITY® operating system, this solution defends against security threats by eliminating vulnerabilities commonly found in the core software of deployed telecom systems. Green Hills Software’s Platform for Secure Networking offers commercial-grade, field-proven, dual IPv4/IPv6 routing stack, cryptographic communications suite, and Layer 3 routing protocols including OSPF, BGP, and RIP. This high-performance integrated solution is optimized for both symmetric and asymmetric multiprocessing on Freescale’s QorIQ platform.
“Our customers are increasingly interested in the security of their networking equipment and other connected devices,” said Lynelle McKay, senior vice president and general manager of Freescale’s Networking and Multimedia Group. “By applying Green Hills Software’s extensive security and networking experience to Freescale’s QorIQ platforms, customers are empowered to create high-performance, highly available, secure networked systems.”
“Our customers are increasingly interested in the security of their networking equipment and other connected devices,” said Lynelle McKay, senior vice president and general manager of Freescale’s Networking and Multimedia Group. “By applying Green Hills Software’s extensive security and networking experience to Freescale’s QorIQ platforms, customers are empowered to create high-performance, highly available, secure networked systems.”
Monday, July 7, 2008
Cores secure FPGA designs
AES1 and GCM1 IP cores enable FPGA vendors to add encryption to their designs using less than 15% of an RT54SX72S device.
IP Cores now offers AES and AES/GCM IP cores supporting the FIPS-197, ieee802.1ae and P1619.1 standards AES1 and GCM1 IP cores enable FPGA vendors to add encryption to their designs using less than 15% of the RT54SX72S device .AES1-8 and GCM1-8 cores are ideally suited for security implementations that fit into compact low-power, rad-hard and rad-tolerant devices", says Dmitri Varsanofiev, CTO of IP Cores.
"Our cores enable customers to implement encryption designs with datarates in the range of 10Mbit/s to more than 400Mbit/s utilising just a small fraction of a typical Actel FPGA".Advanced Encryption Standard in Galois/Counter Mode (GCM-AES) is used the ieee-standards for layer 2 transport security and P1619.1 for tape encryption.
Addressing the market demand for ultracompact AES crypto solutions for Actel FPAG market, IP Cores had shipped its AES1 and GCM1 cores targeted for RTSX, ProASIC, ProASIC3, Igloo and ProASIC Plus APA FPGA families. AES1 and GCM1 configurations support AES and AES/GCM encryption and decryption respectively with throughputs exceeding 100Mbit/s in a single core.
IP Cores' expanding portfolio of security and DSP IP cores includes AES and AES/GCM cores available in multiple configurations to meet specific throughput, power and FPGA resource utilisation targets.
News release from IPCORES
IP Cores now offers AES and AES/GCM IP cores supporting the FIPS-197, ieee802.1ae and P1619.1 standards AES1 and GCM1 IP cores enable FPGA vendors to add encryption to their designs using less than 15% of the RT54SX72S device .AES1-8 and GCM1-8 cores are ideally suited for security implementations that fit into compact low-power, rad-hard and rad-tolerant devices", says Dmitri Varsanofiev, CTO of IP Cores.
"Our cores enable customers to implement encryption designs with datarates in the range of 10Mbit/s to more than 400Mbit/s utilising just a small fraction of a typical Actel FPGA".Advanced Encryption Standard in Galois/Counter Mode (GCM-AES) is used the ieee-standards for layer 2 transport security and P1619.1 for tape encryption.
Addressing the market demand for ultracompact AES crypto solutions for Actel FPAG market, IP Cores had shipped its AES1 and GCM1 cores targeted for RTSX, ProASIC, ProASIC3, Igloo and ProASIC Plus APA FPGA families. AES1 and GCM1 configurations support AES and AES/GCM encryption and decryption respectively with throughputs exceeding 100Mbit/s in a single core.
IP Cores' expanding portfolio of security and DSP IP cores includes AES and AES/GCM cores available in multiple configurations to meet specific throughput, power and FPGA resource utilisation targets.
News release from IPCORES
Silicon Logic Engineering Interlaken IP Core
EDA News - 2008.05.06 Late Edition
Silicon Logic Engineering Inc. (SLE) recently announced the availability of a new 150Gb/s high speed Interlaken protocol IP core for use in ASIC designs. SLE's new Interlaken IP Core is now available with more than twice the performance of the standard 60Gb/s version. This new high-speed core delivers the performance and bandwidth that new designs require, now with higher data transfer rates. The higher performance Interlaken Core is fully scalable, ideally suited for multiple generations of future network switches, routers and storage equipment. The scalability is achieved through the combination of the SERDES speed (3.125Gbps to 6.375Gbps) and a variable number of SERDES lanes (1 to 24).
Designed and tested to be easily synthesizable into any ASIC technology, SLE's Interlaken IP Core was built to work with off-the-shelf SERDES from most leading technology vendors. Using the vendor specific proven SERDES allows SLE customers to quickly integrate the Interlaken IP Core into the customer's technology of choice.
SLE has shipped the new 150Gb/s core and customers reported that the IP delivers the highest data transfer rates available on the market today
Silicon Logic Engineering Inc. (SLE) recently announced the availability of a new 150Gb/s high speed Interlaken protocol IP core for use in ASIC designs. SLE's new Interlaken IP Core is now available with more than twice the performance of the standard 60Gb/s version. This new high-speed core delivers the performance and bandwidth that new designs require, now with higher data transfer rates. The higher performance Interlaken Core is fully scalable, ideally suited for multiple generations of future network switches, routers and storage equipment. The scalability is achieved through the combination of the SERDES speed (3.125Gbps to 6.375Gbps) and a variable number of SERDES lanes (1 to 24).
Designed and tested to be easily synthesizable into any ASIC technology, SLE's Interlaken IP Core was built to work with off-the-shelf SERDES from most leading technology vendors. Using the vendor specific proven SERDES allows SLE customers to quickly integrate the Interlaken IP Core into the customer's technology of choice.
SLE has shipped the new 150Gb/s core and customers reported that the IP delivers the highest data transfer rates available on the market today
IP Cores
An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array ( FPGA ) or application-specific integrated circuit ( ASIC ) for a product. As essential elements of design reuse , IP cores are part of the growing electronic design automation ( EDA ) industry trend towards repeated use of previously designed components. Ideally, an IP core should be entirely portable - that is, able to easily be inserted into any vendor technology or design methodology. Universal Asynchronous Receiver/Transmitter ( UART s), central processing units ( CPU s), Ethernet controllers, and PCI interfaces are all examples of IP cores.
IP cores fall into one of three categories: hard cores , firm cores , or soft cores . Hard cores are physical manifestations of the IP design. These are best for plug-and-play applications, and are less portable and flexible than the other two types of cores. Like the hard cores, firm (sometimes called semi-hard ) cores also carry placement data but are configurable to various applications. The most flexible of the three, soft cores exist either as a netlist (a list of the logic gate s and associated interconnections making up an integrated circuit ) or hardware description language ( HDL ) code.
A number of organizations, such as the Free IP Project and Open Cores, have formed to promote open sharing of IP cores.
IP cores fall into one of three categories: hard cores , firm cores , or soft cores . Hard cores are physical manifestations of the IP design. These are best for plug-and-play applications, and are less portable and flexible than the other two types of cores. Like the hard cores, firm (sometimes called semi-hard ) cores also carry placement data but are configurable to various applications. The most flexible of the three, soft cores exist either as a netlist (a list of the logic gate s and associated interconnections making up an integrated circuit ) or hardware description language ( HDL ) code.
A number of organizations, such as the Free IP Project and Open Cores, have formed to promote open sharing of IP cores.
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