Cores secure FPGA designs

AES1 and GCM1 IP cores enable FPGA vendors to add encryption to their designs using less than 15% of an RT54SX72S device.

IP Cores now offers AES and AES/GCM IP cores supporting the FIPS-197, ieee802.1ae and P1619.1 standards AES1 and GCM1 IP cores enable FPGA vendors to add encryption to their designs using less than 15% of the RT54SX72S device .AES1-8 and GCM1-8 cores are ideally suited for security implementations that fit into compact low-power, rad-hard and rad-tolerant devices", says Dmitri Varsanofiev, CTO of IP Cores.

"Our cores enable customers to implement encryption designs with datarates in the range of 10Mbit/s to more than 400Mbit/s utilising just a small fraction of a typical Actel FPGA".Advanced Encryption Standard in Galois/Counter Mode (GCM-AES) is used the ieee-standards for layer 2 transport security and P1619.1 for tape encryption.

Addressing the market demand for ultracompact AES crypto solutions for Actel FPAG market, IP Cores had shipped its AES1 and GCM1 cores targeted for RTSX, ProASIC, ProASIC3, Igloo and ProASIC Plus APA FPGA families. AES1 and GCM1 configurations support AES and AES/GCM encryption and decryption respectively with throughputs exceeding 100Mbit/s in a single core.

IP Cores' expanding portfolio of security and DSP IP cores includes AES and AES/GCM cores available in multiple configurations to meet specific throughput, power and FPGA resource utilisation targets.

News release from IPCORES