On2 Technologies Announces New High Definition Hardware Encoder IP

The Hantro™ 7280 enables real-time video encoding up to 1280 x 1024 resolution for low-power chipsets

On2 Technologies (AMEX: ONT), the leader in video compression solutions, announced today the availability of the Hantro 7280 encoder Register Transfer Level (RTL) design. Supporting MPEG-4, H.263 and H.264 video, along with 16MP JPEG, the encoder is targeted for chipsets intended for devices with very low-power requirements such as: portable video cameras, mobile phones, remote security cameras, laptops and webcams. With a maximum resolution of 1280x1024 at 30 fps, the Hantro 7280 introduces a new level of performance and functionality.

Following the Hantro 6280, which was licensed by more than 15 leading chip manufacturers, the encoder brings further speed improvements to achieve resolutions up to 1280x1024 at 30 fps. Easily encoding full 720p H.264 at 30 fps in only 180 MHz clock frequency, the 7280 brings ultra-high performance to 65 nm and 90 nm low-power chipsets. Placing a CPU load of less than 1MHz, the Hantro 7280 allows even an entry level ARM9-based chipset to encode real-time HD H.264 video with plenty of headroom to spare. The new encoder also incorporates proprietary image stabilization technology which reduces the effects of camera shake prior to encoding resulting in higher quality video with better compression.

Optimized for rapid integration with ARM, MIPS and other embedded CPU and DSP cores, the Hantro 7280 marries high performance with ultra low-power and efficient silicon utilization. Silicon area can be further optimized for unique applications by selecting only the formats and screen resolutions required with area reduced to as small as 0.19 square millimeters per 139,000 gates. Additional area savings can be gained in a full codec solution by sharing internal memories with the Hantro 8190 multi-format decoder.

“For portable devices, battery-life is a critical success factor and manufacturers seek to optimize in every aspect.” says Eero Kaikkonen, Chief Marketing Officer at On2. “The 7280 requires only 12 mW to encode VGA H.264 in real-time. Although in practice it is not possible, theoretically an ARM 11 would require as much as 500mW to achieve the same performance.”

The Hantro 7280 is available now for licensing from On2. The product comes complete with RTL source code for VHDL or Verilog, an RTL test bench and test data, ANSI C driver source code and complete technical documentation.

ChipX Adds More Than 60 Analog Functions to IP Portfolio

Easy to use, silicon proven, industrial-grade analog building blocks enable low-risk analog circuit integration in industrial, medical, military and aerospace mixed-signal ASICs

Santa Clara – September 15, 2008 – ChipX, Inc, a mixed-signal company providing the industry's broadest offering of low-risk ASIC solutions, today announced the addition of over 60 industrial-grade analog building blocks to its line-up of analog and mixed-signal IP. Following the company’s digital to analog converter family announcement in June 2008, ChipX is continuing on its quest to increase its analog and mixed-signal ASIC capabilities with a focus on Medical, Industrial, Military and Aerospace applications

Designed for signal conditioning, on-chip references, clocking, controlled reset, Input/Output and a variety of other analog functions, the analog building blocks are ideal for system-chip designs used in medical devices, industrial products, military and aerospace applications. Fully-characterized for Industrial temperature in high-volume CMOS process geometries of ChipX foundry partners, the analog building blocks can be combined with other proven ChipX IP or trusted 3rd party IP for System-on-Chip (SoC) designs.

“Our system architecture and analog team works with customers to come up with the best balance between on-chip and off-chip analog functions,” said Elie Massabki, Vice President of Marketing for ChipX. By using our proven catalog of analog building blocks and other IP, customers can integrate substantial parts of their system on one mixed-signal device to reduce system cost and lower implementation risk.”

Analog Building Block Catalog

The ChipX analog building block catalog consists of many general purpose functions, available in 250nm, 180nm and 130nm processes. Building blocks include analog switches and multiplexers, charge pumps, comparators, self-calibrated termination, reference resistors, reference voltage and reference current generators, oscillator circuits, power-on-reset generators, operational amplifiers and various I/Os including HSTL, SSTL 1.5/1.8/2.5/3.3, LVPECL and LVDS.

Each of the analog building block family members includes simulation models, extensive data sheets, and full design information. They can be integrated with the full range of ChipX building blocks – including 10-bit, 210Msps DAC, USB 2.0, PCI Express, DDR/DDR2, ARM(926) or BA12/22 processors to create a System on Chip (SoC) – in mixed-signal Hybrid ASIC, Embedded Array or Standard Cell products today.

About ChipX

ChipX, Inc. is a Mixed-Signal ASIC company with the broadest offering of value-added ASIC solutions, including Standard Cell, Structured ASIC and Hybrid ASIC technology. ChipX has unique expertise in PCI Express, USB 2.0, DDR/DDR2 and data conversion mixed-signal cores; all are silicon proven and certified and they can be integrated in customers’ ASICs with a record first-time to market success. ChipX products are widely used in industrial applications, medical equipment and military/aerospace systems. Headquartered in Santa Clara, CA, ChipX is a privately held corporation, with a Research and Development subsidiary in Israel. Investors include Elron Electronic Industries, Ltd. (NASDQ: ELRN),VantagePoint Venture Partners, Wasserstein Venture Capital, UMC and Needham Capital Partners.

To develop or buy a Verification IP

Atul Bhatia, Director, nSys Design Systems

Independent Interpretation

The most important benefit of buying the VIP rather than making it is that a commercial VIP provides a totally independent, clear and unambiguous interpretation of the specifications of a protocol for which it is designed. Until the time when the specifications themselves are written such that they have no ambiguity, this independent interpretation is invaluable. It gets even more important when the specifications are those of a complex protocol. In case the commercial VIP is already proven by use with RTL designs of other users, the value increases to several times of its cost to the user. This is because the user is assured inter-operability and compliance due to the use of this VIP with other designs.

Availability of Test Suites

If the VIP is available not only with the Bus Function Models, Monitor and Protocol Checker but also with Test Suites, then the user is able to save considerable time that would have been spent in writing the test cases that are available as part of the Test Suites. Not only are the test cases difficult to identify and time-consuming, most engineers write them grudgingly. Availability of test cases in source code makes it easier to modify and create additional cases unique to the user’s designs.

Packaging

Just as a home-made dish cannot be packaged as attractively as the one that is available from a restaurant, an in-house VIP will also not be packaged as well as a commercial VIP. Some of the distinct features of the packaging that are very difficult to incorporate in an in-house VIP are: availability of a well-documented User Manual, Flash-based tutorials, comprehensive FAQs based upon queries faced by existing users, a self-service bug tracking portal, Application notes and a well designed GUI. In case the VIP provider is offering a family of VIPs, the additional features of packaging would be: consistency of interface, installation, operation, and documentation across the VIP family. Since the APIs for a family would be well thought out and consistent across the family of VIP, it would reduce the requirement of learning the API while using additional interfaces.

FPGA Designs

At the other end of the spectrum of the develop-or-buy decision are the FPGA developers who do not even consider using simulation for verification. They feel that they would find the bugs at the system level in any case and the bug would just require a change in the RTL rather than throw away the chip as would be the case for an ASIC developer. This belittles the complexity of FPGA designs brought about by increase in their size. Fortunately, FPGA developers are becoming aware of this and have begun verifying their designs extensively in simulation too. Especially since it is very easy to compute that the cost of a license of a commercial VIP may be less than the cost of one engineering man-month. We have not factored in the impact of the cost of delay in product which will be many times this cost.

RTL IP

One of the ways of overcoming the well known productivity gap is the use of Design or RTL IP. A 2002 study by Collett International Research revealed that 14 percent of all chips that failed had bugs in reused components or imported IP. The other key problem while using an IP is that its integration with rest of the design has to be thoroughly tested. Thus a VIP should be able to verify the IP at the block level and also provide features for System level verification to ensure the correctness of integration of the IP with rest of the design.

Bundled VIP

Some situations when the develop-or-buy decisions get difficult to make are when an RTL IP has been used for a while and can be expected to be bug-free or when an RTL IP is available with a VIP. It has been observed that even if an RTL IP is field-proven, it may still have several bugs that are brought out by a new design (as luck would have it). A free VIP that may be available with RTL IP unless it is from a 3rd party vendor is not good enough for use in a commercial project. In the case when a 3rd party VIP is available bundled with the IP, it is likely to have a reduced feature set sufficient to demonstrate the working of the IP and the VIP while the features required to perform verification of the IP as well as its integration with the rest of the design may not be available. In fact, the extra effort spent in using the free or scaled-down VIP is several times the cost of a good 3rd party full feature VIP.

Conclusion

Verification productivity that is required to meet the challenges of tomorrow can only be met by incorporating widely used and proven VIPs in the verification flow. A family of VIPs having consistency of interface as well as look and feel increases this productivity across projects. The case for developing a VIP can only be made for proprietary interfaces. For all other interfaces, it is better to buy rather than develop a VIP.

An Industry First: 8-Channel Analog Front End IC

IQ Analog now brings to market an industry first: an 8-channel, low power, high-performance Analog Front End Integrated Circuit (IC) for multi-channel applications such as MIMO radios.


After three years of development, IQ Analog announces the arrival of the IQA-F430 Octal Analog Front End (AFE), ushering in the next generation mixed signal front end platform for wireless and communication applications. According to Mike Kappes, President & CEO of IQ Analog, the IQA-F430 Octal AFE makes real the promise of integrating multiple discrete AFE devices into a single, cost effective and low power solution.


“IQ Analog is uniquely positioned to now offer multi-channel integration within low cost packaging constraints…we immediately address the wireless infrastructure market with a single IC that replaces the multi-chip solutions in use today…..” stated Kappes. As an example, Kappes points out that a typical MIMO configuration consists of 4 x 2 channel AFEs; this configuration is replaced with just a single, 8 channel IC chip from IQ Analog. In this system solution, not only is cost mitigated by the F430, but power consumption is radically minimized. IQ Analog’s F430 measures at 30mW per channel versus 300mW per channel for existing market offerings. Another hallmark of IQ Analog mixed signal technology; phenomenally small die size. The 8 way F430 is 16mm2, about 40% the size of comparable 2 channel AFEs.


The IQA F430 AFE is characterized by 8 independent 12-bit 80-Msps analog-to-digital converters (ADC’s) and 8 independent 12-bit 20-MHz bandwidth digital-to-analog converters (DAC’s) for the main signal paths and 8 auxiliary 12-bit 300-Ksps ADC’s and 8 auxiliary 12-bit 300-Ksps DAC’s for ancillary functions. The F430 is currently fabricated in a 130nm CMOS process; Kappes and his team plan to move to 65nm before the end of 2008.


About IQ Analog

IQ Analog is a privately held fabless semiconductor company headquartered in San Diego, CA. The company was founded by industry veterans who previously led engineering efforts at leading System-on-Chip (SoC) companies including Broadcom, Conexant, Innovent, and Brooktree. In addition to its newly released IC product family, the company offers analog interface components including a range of ADCs and AFEs in 180nm /130nm/90nm/65nm. IQ Analog provides world class design and customization services to support its IP portfolio. For more information, visit www.iqanalog.com or contact info@iqanalog.com.

IP Cores for Education

In electronic design and electronic design automation, an intellectual property (IP) block—or IP core—is a unit of reusable design, the use of which has been licensed to a third party. The term is derived from the licensing of the intellectual property rights, such as patents and copyrights, that subsist in the design.

IP cores are for hardware design what libraries are for computer programming. They are typically used much in the style and manner of a discrete integrated circuit on a PCB, where the "circuit board" is a larger ASIC or FPGA design. An IP core commonly takes the form of a computer program written in some HDL—such as Verilog, VHDL, or SystemC—but it can also be a netlist or physical layout, especially in analog electronics.

Altera provides a library of SOPC Builder components (IP cores), which are listed in the table below, for all I/O devices on the DE1 and DE2 boards. You can use these components as part of the SOPC Builder tool in the Quartus® II software. They allow you to easily create Nios® II systems that can access the I/O devices on the DE1 and DE2 boards. Also provided are the associated software drivers that you can incorporate into an Altera® Debug Client project (or an Altera Nios II IDE project). You can install the components in the library using the installer found in the table or download individual IP cores independently. If the IP cores are downloaded independently, you must place them in your project directory or in the sopc_builder\components within the Quartus II install path.

Note: The University Program IP cores are still under development. Several of the cores are available in beta release version. The beta release is supported directly by the Altera Debug Client.


Table 1. University Program IP Cores
IP Cores Description PDF ZIP Development Board Supported
Embedded Processors
Nios II Altera's embedded soft processor
Nios II DE1, DE2
IP Core Bundle
Installer Installs all the available IP cores. The IP cores are listed below. EXE DE1, DE2
Release Notes Description of releases to date TXT
Memory Controller
SRAM Provides read/write access to the SRAM chip PDF ZIP DE1, DE2
SDRAM Provides read/write access to the SDRAM chip and also refreshes the chip automatically PDF ZIP DE1, DE2
FLASH Not available PDF ZIP DE1, DE2
SD Card Not available PDF ZIP DE1, DE2
Communication
RS232 UART Provides a UART over the RS232 port PDF ZIP DE1, DE2
JTAG UART Provides a UART over the JTAG PDF DE1, DE2
Ethernet Not available PDF ZIP DE2
IrDA Provides a UART over the IrDA port PDF ZIP DE2
USB Not available PDF ZIP DE2
Audio/Video
Audio/Video Configuration Automatically configures the audio and video chip PDF ZIP DE1, DE2
Audio In/Out Provides two FIFOs for audio data PDF ZIP DE1, DE2
Video Out Creates timing information for VGA display and has frame buffers for storing picture information PDF ZIP DE1, DE2
Video In Not available PDF ZIP DE2
Input/Output
Parallel Port A generic parallel input/output interface PDF ZIP DE1, DE2
PS/2 Port Serial connection for the PS/2 port PDF ZIP DE1, DE2
16x2 LCD Character Display Connection to the LCD character display PDF ZIP DE2
Avalon® to External Bus Bridge A bus-like interface for a slave device PDF ZIP DE1, DE2
External Bus to Avalon Bridge A bus-like interface for a master device PDF ZIP DE1, DE2

The above IP cores have been developed to support Altera's University Program and its DE1 and DE2 development and education boards. It is important to note that Altera provides a wide range of IP cores to implement industry-standard designs (such as a USB controller or echo cancellation circuitry) and speed system engineering. Altera IP cores are designed to take advantage of the unique features of FPGAs.

Altera offers IP megafunctions for the following technology types:

Embedded Processors (Nios II processors, microcontrollers)
Interfaces and Peripherals (DDR2, PCI, PCI Express)
Digital Signal Processing (fast Fourier transform)
Communications (various physical layers)
View the full listing of available IP cores at the Altera IP MegaStore™.

Commercial IP Core Requests
The Altera University Program provides Altera-developed IP at no charge to qualified research projects at universities. Please contact university@altera.com for more information.

Recore Systems New IP

Recore Systems licenses innovative IP for creating advanced digital signal processing platform chips. Recore’s Montium® technology comprises processor cores, design tools for easy integration in customer solutions and ready-to-use applications. Recore offers application implementations for Montium based platforms, IDE tools and hardware IPs.

Recore’s technology enables ultra energy-efficient digital signal processing in products such as cell phones, digital radios/TVs and infotainment and navigation systems. Reuse of Recore’s IP alleviates the avalanching design complexity and costs of today’s chip development. Montium technology allows time multiplexing of different functions on the same hardware and offers a unique combination of flexibility, high performance, low power and low costs.

An excellent engineering team is devoted to create supreme systems-on-chip, with exceptional power and performance characteristics. Recore attracts the best people into all levels of the organization and encourages a stimulating environment, with strong links to leading research centers.


3 Product(s) Listed



Part Number Product Description
Montium DAB/DAB+ Viterbi Decoder Soft IP core implementation of the Viterbi algorithm for Montium tile processors optimized for DAB/DAB+ applications
Montium® FFT/IFFT IP Core FFT/IFFT implementation for Montium Tile Processors
Montium Tile Processor (TP) Dynamically Reconfigurable Digital Signal Processing Tile Processor

HDL Design House New IP

HDL Design House is a fast growing privately owned company focused on providing synthesizable VHDL/Verilog IP cores, ASIC (SoC) or FPGA design and design verification services.

HDL Design House was incorporated in March of 1999 with the mission to offer world class hardware design services to international customers. The founders have more then 10 years as consulting experts in ASIC/FPGA design for local and international customers. The strong experience and professional background acquired during this period, supplemented by customer satisfaction, encouraged them to found their own company and start to offer hardware design services.

The company has strong background in telecommunications, DSP, computer architecture, high performance computer arithmetic, and different communication protocols. Actively cooperating with USA companies on leading high-tech projects, HDL Design House engineering staff acquired and developed world class expertise in complex ASIC/FPGA design and design management, design verification, and related skills.

HDL Design House has internal IP core development program. Still it can develop IP cores according to the customer specification.

We favor long-term relationship with our customers.


11 Product(s) Listed



Part Number Product Description
HIP 3200 UniPro Soft IP Core
HIP 2900 BCH Codec
HIP 4000 Golay Encoder/Decoder IP Core
HIP 2400 Reed Solomon Encoder IP Core
HIP 2500 Reed Solomon Decoder IP Core
HIP 3000 APB SPI Lite IP Core
HMC FIDWT 39510 Forward and Inverse Discrete Wavelet Transform
HMC FFT 31510 1024-Point Complex FFT/IFFT
HIP 1100 DES/TDES - Full hardware implementation of NIST FIPS PUB 46-3 algorithm (DES/TDES). OCP/AMBA bus interfaces
HIP 1000 AES - Full hardware implementation of NIST FIPS PUB 197 algorithm. 128 bit data and programable 128/192/256 key length
IEEE 1284 IEEE 1284 Parallel Port Controller